PCB layout and electromagnetic compatibility for MB90 series microcontrollers. Little secrets of routing boards with operational and instrumentation amplifiers
IN this section we look at how to avoid digital signal distortion associated with its transmission along the conductor on the printed circuit board. Although this is primarily a task for the circuit engineer, the PCB designer is also often to blame for problems with signal transmission on the board, as well as crosstalk and crosstalk occurring on the board.
Why is the signal distorted during transmission?
First of all, distortion is characteristic of high-frequency signals, with a frequency of 1 GHz or more. This is due to the effects of resonances and reflections on individual wire segments, vias, fan-outs on the board, and at the receiver inputs. However, the problem is that signals with a frequency of up to 500 MHz, typical for standard digital circuits, as we will see later, can often be significantly distorted, which means they can also be classified as high-frequency.
What is the idea of transmission without distortion?
The principle of signal transmission without distortion is that the conductor is made as a transmission line (or “long line”) with a given characteristic (wave) impedance, i.e. impedance Z 0 , the same along the entire length from the source to the signal receiver, which ensures the homogeneity of the line. The second requirement is the consistency of the line with the source and receiver of the signal. Unlike a conventional conductor, such a transmission line does not lead to resonance, distortion and reflection during signal transmission, no matter how long it is. Transmission lines can be easily implemented on a printed circuit board by using materials with known parameters and ensuring the required dimensions of the printed pattern elements. There are serial and parallel line matching, and it is necessary to use certain matching resistors at the source output and/or signal receiver input. The transmission lines formed on the board can, of course, be extended outside the board using connectors and cables with controlled characteristic impedance Z 0 .
For which signals does distortion become significant?
By comparing the length of the conductor on the board with the wavelength that the highest frequency component has transmitted signal(when distributed, for example, in FR4 material), the so-called electrical length of the conductor can be determined. The electrical length can be expressed in fractions of the minimum wavelength or in fractions of its inverse value - the front duration. If the conductor has too large an electrical length, then to prevent excessive signal distortion, this conductor must be configured as a transmission line. Note that when transmitting high-frequency signals, transmission lines should be used not only to reduce distortion, but also to reduce the level of electromagnetic radiation (EMR).
Rule of "half the duration of the front"
A rough rule is that the conductor is "electrically long" (what is called in electrical engineering "long line"), if the time it takes for the signal front to pass from the source to the farthest receiver exceeds half the signal front time. It is in this case that reflections in the line can significantly distort the signal front. Let's assume that the device contains chips with a rise time of 2 ns (for example, according to the documentation for the FastTTL series). Dielectric constant of PCB material (FR4) on high frequencies is close to 4.0, which gives the speed of the front about 50% of the speed of light, or 1.5.10 8 m/s. This corresponds to a front propagation time of 6.7 ps/mm. With this speed, the front will travel about 300 mm in 2 ns. From this we can conclude that for such signals "transmission lines" should only be used if the conductor length exceeds half of this distance - that is, 150 mm.
Unfortunately, this is the wrong answer. The "half rise time" rule is too simplistic and can lead to problems if its shortcomings are not taken into account.
Problems with the simplified approach
The data on the rise time given in the documentation for the microcircuits reflects the maximum value, and often real time switching is significantly less (say, it can be 3-4 times less than the “maximum” one, and it is hardly possible to guarantee that it will not change from batch to batch of chips). Moreover, the inevitable capacitive component of the load (from the line-connected IC inputs) reduces the signal propagation speed compared to the design speed achievable on a bare circuit board. Therefore, to achieve adequate transmitted signal integrity, transmission lines should be used with much shorter conductors than the previously described rule suggests. It can be shown that for signals with a rise time (according to the documentation) of 2 ns, it is advisable to use transmission lines for conductors whose length exceeds only 30 mm (and sometimes less)! This especially applies to signals that carry a synchronization or gating function. It is precisely these signals that are characterized by problems associated with “false positives,” “recalculation,” “recording of incorrect data,” and others.
How to design transmission lines?
There are many publications devoted to what types of transmission lines there can be, how to design them on a printed circuit board, and how to check their parameters. In particular, the IEC 1188-1-2: 1988 standard provides detailed guidance in this regard. There are also many software products available that allow you to select transmission line design and PCB structure. Majority modern systems design printed circuit boards come with built-in programs that allow the designer to design transmission lines with specified parameters. Examples include programs such as AppCAD, CITS25, TXLine. Most full capabilities provide software products from Polar Instruments.
Examples of transmission lines
As examples, consider the most simple types transmission lines.
How to design the transmission line in the best way?
The highest speed (or most critical) signals should be in layers adjacent to the ground plane (GND), preferably one that is paired with the decoupling power plane. Less critical signals can be applied to power plans if those plans are adequately decoupled and are not very noisy. Each such power plan must be associated with the microcircuit from which or to which this signal is received. The best noise immunity and EMC are provided by strip lines drawn between two GND plans, each of which is paired with its own power plan for decoupling.
The transmission line must not have holes, breaks or splits in any of the reference plans to which it is drawn, as this will lead to significant changes in Z 0 . Moreover, the strip line should be as far as possible from any discontinuity in the plan or from the edge of the supporting plan, and this distance should not be less than ten times the width of the conductor. Adjacent transmission lines must be separated by at least three conductor widths to eliminate crosstalk. Very critical or "aggressive" signals (such as communication with a radio antenna) can benefit from EMC by using a symmetrical line with two rows of closely spaced vias, as if blocking it from other conductors and creating a coaxial structure in the printed circuit board. However, for such structures, Z 0 is calculated using different formulas.
How can you reduce the cost of a project?
The types of transmission lines described above almost always require the use of a multilayer board, and therefore may not be applicable to the creation of mass-produced low-end products. price category(although at high volumes, 4-layer PCBs are only 20-30% more expensive than double-sided). However, for low-cost projects, line types such as balanced (uniform) or coplanar are also used, which can be constructed on a single-layer board. It should be borne in mind that single-layer types of transmission lines occupy several times more area on the board than microstrip and stripline lines. In addition, while saving on the cost of the printed circuit board, you will be forced to pay more for additional device shielding and noise filtering. Eat general rule, which states that solving EMC problems at the product packaging level costs 10-100 times more than solving the same problem at the printed circuit board level.
Therefore, when reducing your development budget by cutting the number of PCB layers, be prepared to spend Extra time and money for several iterations of ordering sample boards to ensure the required level of signal integrity and EMC.
How to weaken negative effect from changing layers?
According to standard wiring rules, there is at least one decoupling capacitor near each chip, so we can change the layer near the chip. However, the total length of the segments that are not located in the "strip" layer must be taken into account. A rough rule is that the total electrical length of these segments should not exceed one-eighth of the rise time. If too large a change in Z 0 may occur on any of these segments (for example, when using ZIF sockets or other types of sockets for microcircuits), it is better to strive to minimize this length to one tenth of the rise time. Use this rule to determine the maximum allowable total length of non-standardized segments and try to minimize it within these limits as much as possible.
Based on this, for signals with a rise time (according to the documentation) of 2 ns, we must change the layer no further than 10 mm from the center of the microcircuit or from the center of the matching resistor. This rule was developed taking into account a 4-fold margin for the fact that the actual switching time may be significantly less than the maximum according to the documentation. At approximately the same distance (no more) from the place where the layers are changed, there should be at least one decoupling capacitor connecting the corresponding ground and power plans. Such small distances are difficult to achieve when using microcircuits big size, so there are trade-offs in the layout of modern high-speed circuits. However, this rule justifies the fact that small-sized microcircuits are preferable in high-speed circuits, and explains the fact of the rapid development of BGA and flip-chip technologies, which minimize the signal path from the conductor on the board to the chip of the microcircuit.
Simulation and testing of prototypes
Due to the availability of many chip options and more more of their application, some engineers may find these rules of thumb to be insufficiently precise, and some will find them exaggerated, but that is the role of “rules of thumb” - they are just a rough approximation to intuitively design devices that work correctly.
Nowadays, computer modeling tools are becoming more and more accessible and advanced. They allow you to calculate signal integrity parameters, EMC, depending on the actual layer structure and signal routing. Of course, their use will give more accurate results than our rough approximations, so we recommend using them as fully as possible computer modelling. However, do not forget that the actual switching time of microcircuits can be significantly shorter than that indicated in the documentation, and this can lead to incorrect results, so make sure that the model of the output and input stages corresponds to reality.
The next step is to check the passage of the critical signal on the first “prototype” sample of the printed circuit board, using a high-frequency oscilloscope. You need to make sure that the waveform is not distorted as it travels along the entire length of the circuit board, and just following the above rules is unlikely to give an excellent result the first time, although it may be quite good. Using an RF Electromagnetic Field Analyzer, or Emission Spectrum Analyzer, can be another way to examine signal integrity and EMC issues at the "prototype" PCB level. Methods for such analysis are not the topic of this article.
Even if you use complex circuit simulation, don't neglect signal integrity and EMC testing on your very first PCB prototypes.
Providing wave impedances at the PCB manufacturing stage
A typical FR4 material intended for the manufacture of printed circuit boards has a dielectric constant (E r) value of about 3.8...4.2 at 1 GHz. Real values E r can fluctuate within ±25%. There are FR4 materials that have an E r value that is rated and guaranteed by the supplier and are not much more expensive than conventional materials, but PCB manufacturers are not required to use "rated" FR4 grades unless specifically specified in the PCB order.
PCB manufacturers work with standard dielectric thicknesses (“prepregs” and “laminates”), and their thickness in each layer must be determined before the board is put into production, taking into account thickness tolerances (about ±10%). To ensure a given Z 0, for a certain dielectric thickness, you can select the appropriate conductor width. For some manufacturers it is necessary to indicate the actual required width of the conductor, for others - with a margin for undercuts, which can reach 25-50 microns relative to the nominal width. The best option is an indication to the manufacturer what width of the conductor in which layers is designed taking into account the provision of a given Z 0. In this case, the manufacturer can adjust the conductor width and layer structure to ensure specified parameters in accordance with its production technology. In addition, the manufacturer measures the actual wave resistance on each factory blank and itself rejects boards on which Z 0 does not fall within the tolerance of ±10% or more precisely.
For signals above 1 GHz, it may be necessary to use higher frequency materials with better stability and other dielectric properties (such as Duroid from Rogers, etc.).
Literature
1. Design Techniques for EMC & Signal Integrity, Eur Ing Keith Armstrong.
2. IEC 61188-1-2: 1998 Printed Boards and Printed Board Assemblies - Design and use. Part 1-2: Generic Requirements - Controlled Impedance, www.iec.ch.
3. Design of multilayer printed circuit boards of high complexity. Seminar PCB technology, 2006.
4. http://library.espec.ws/books/chooseant/CHAPTER6/6-1.htm
5. Hardware design. Walt Kester.
- Minimize RF bus lengths
- Separate the power and ground buses between the analog and digital parts of the circuit
- Do not break earth polygons with high-frequency conductors
Definitions:
Electromagnetic compatibility (EMC): the ability in the process of functioning not to make an excessive contribution to the environment electromagnetic radiation. When this condition is met, all electronic components work together correctly.
Electromagnetic interference (EMI): electromagnetic energy, emitted by one device, which can lead to a violation of the quality characteristics of another device.
Electromagnetic immunity, EMPU (Electromagnetic immunity, or susceptibility, EMS): tolerance (resistance) to the effects of electromagnetic energy.
Design with taking into account EMC: 4 main rules
The problem with rules: the more rules you have, the harder it is to follow them all. The prioritization of their implementation is different.
Suppose, when creating a multilayer printed circuit board, you need to route a high-frequency signal from an analog component to a digital one. Naturally, you want to minimize the likelihood of an electromagnetic compatibility (EMC) problem. After searching the Internet, you find three recommendations that seem to be relevant to your situation:
Your vision of three possible options wiring is shown in Fig. 1.
In the first case, the routes are routed directly between the two components, and the ground polygon remains solid. In the second case, a gap is formed in the polygon, and the tracks pass across this gap. In the third case, the routes are laid along the gap in the polygon.
In each of these three cases, one of the above rules is violated. Are these alternative cases equally good because they satisfy two of the three rules? Are they all bad because they each break at least one rule?
These are the questions PCB designers face every day. The right or wrong choice of routing strategy can lead to results in which the board either meets all EMC requirements or has problems with susceptibility to external signals. In this case the choice should be clear, but we will come back to this later
The problems are reduced after the recommendations are prioritized. Design guidelines are only useful if they are well understood and if they form part of a complete strategy. Once designers learn to prioritize guidelines and understand how those guidelines should be used, they can skillfully design good PCBs.
The following are the four main EMC rules based on general features electronics products. In many cases, PCB designers deliberately break one of these rules in an attempt to fulfill more important ones.
Rule 1: Minimize Signal Current Path
This simple rule appears in almost every list of EMC recommendations, but often it is either ignored or downplayed in favor of other recommendations.
Often the PCB designer doesn't even think about where the signal currents flow and prefers to think about signals in terms of voltage, but should be thinking in terms of current.
There are two axioms that every PCB designer should know:
- signal currents always return to their source, i.e. the current path is a loop
- signal currents always use the path with minimal impedance
At frequencies of several megahertz and higher, the signal current path is relatively easy to determine because there is a path with minimal impedance, in general case, the path with minimal inductance. In Fig. Figure 2 shows two components on a printed circuit board. A 50 MHz signal travels along a conductor over the test site from component A to component B.
We know that the same magnitude of signal must propagate back from component B to component A. Let's assume that this current (let's call it return) flows from the terminal of component B, designated GND, to the terminal of component A, also designated GND.
Since the integrity of the polygon is ensured, and the terminals, designated as GND, of both components are located close to each other, this leads to the conclusion that the current will take the shortest path between them (path 1). However, this is not correct. High frequency currents choose the path of least inductance (or the path with the minimum loop area, the path of smallest turn). Most of the signal return current flows through the polygon in a narrow path just below the signal trace (path 2).
If the polygon was made for some reason with a cutout as shown in Figure 3, then cutout 1 would have little effect on signal integrity and emission. Another cutout 2 may lead to significant problems; it conflicts with recommendation 2. The loop area increases significantly; reverse currents so intense that they flow along the rupture boundary.
On low frequencies(generally kHz and below), the path of lowest impedance tends to be the path with the lowest signal frequency.
On a mixed-signal board with low-frequency analog and digital components, this can be a problem. Figure 5 illustrates how a well-placed rupture in an earthen landfill can correct the situation by capturing low frequency return currents flowing through the landfill in a designated area.
Rule 2. Do not subdivide the return signal polygon
This is right. We have just shown you an excellent example in a situation where creating a break in the return signal current polygon was the right decision.
However, as typical EMC engineers, we advise you never to do this. Why? Because many of the developments we've encountered by well-informed people have been the result of unintentionally breaking Rule 1 and creating gaps in the return polygons. Moreover, the break was often ineffective and unnecessary. One view is that the analog return signal current should always be isolated from the digital return signal current. This idea arose when analog and
digital circuits
A similar situation arises when wiring tires of automobile or aviation electronic equipment. In such equipment, the digital circuit return currents are often isolated from the general enclosure in order to protect the digital circuits from damage by large LF currents that may flow through the metal structure of the vehicle.
EMI filtering and transient protection typically require connections to the chassis while the signal must be transmitted relative to the digital return bus. When the chassis circuit and digital return current polygons share the same bus, they appear as a single polygon with a discontinuity. This sometimes creates confusion as to which ground something should be connected to. separate component
. In this situation, it is usually a good idea to run the chassis bus and digital return on separate buses. The digital return signal polygon must be solid and occupy the area under all digital components, traces and connectors. The connection to the chassis should be limited to the area of the board near the connectors. Undoubtedly, there are situations where a well-placed break in the return current polygon is required. However, the most reliable method is one continuous polygon for all return signal currents. In cases where a separate low frequency signal susceptible to interference (capable of mixing with other board signals), tracing is used on a separate layer to return this current to the source. In general, never use splitting or cutting in the return signal current polygon. If you are still convinced that a cutout in the polygon is necessary to solve the problem of low-frequency isolation, consult an expert. Do not rely on recommendations from
design
or on applications and do not try to implement a scheme that worked for someone else in another similar design.
Now that we are familiar with the two main rules of EMC, we are ready to revisit the problem in Fig. 1. Which of the alternatives is the best? The first one is the only one that does not contradict the rules. If for some reason (beyond the design desires) a gap in the earthen area was required, then the third wiring option is more acceptable. Tracing along the discontinuity minimizes the signal current loop area. among the board designs we have reviewed and evaluated in our lab. IN simple boards, which should not have any failures under all EMC requirements without any additional cost or effort, good shielding and filtering were negated because this simple rule was broken.
Why is connector placement so important? At frequencies below several hundred megahertz, the wavelength is on the order of a meter or more. The conductors on the board - possible antennas - have a relatively short electrical length and therefore work inefficiently. However, cables or other devices connected to the board can be quite effective antennas.
Signal currents flowing through conductors and returning through solid polygons create small voltage drops between any two points of the polygon. These voltages are proportional to the current flowing through the polygon. When all connectors are placed on one edge of the board, the voltage drop is negligible.
However, high-speed circuit elements placed between connectors can easily create potential differences between the connectors of several millivolts or more. These voltages can induce excitation currents into connected cables, increasing their emissions.
The board that does everything technical requirements When the connectors are located at one edge, it can be an EMC engineer's nightmare if at least one connector with a cable attached is located on the opposite side of the board. Products that exhibit this type of problem (cables carrying voltages induced through an entire polygon) are particularly difficult to restore to normal. Often this requires fairly good shielding. In many cases, this shielding would be completely unnecessary if the connectors were located on one side or in a corner of the board.
Rule 4. Transition time of the control signal
Board running on clock frequency 100 MHz should never meet the requirements when operating at 2 GHz. A well-formed digital signal will have more power on the lower harmonics and not much power on the higher ones. By controlling the transition time of the signal, it is possible to control the signal power at higher harmonics, which is preferable for EMC. Excessively long transient times can lead to signal integrity problems and thermal problems. During the development and design process, a compromise must be made between these competing necessary conditions. Transition time equal to approximately 20% of signal period
, results in an acceptable waveform, reducing problems arising from crosstalk and radiation. Depending on the application, the transition time may be more or less than 20% of the signal period; however, this time should not be uncontrollable.
There are three main ways to change the edges of digital signals:
- use of digital microcircuits of a series whose performance coincides with the required performance,
- placing a resistor or inductor on the ferrite in series with the output signal, and
- placing a capacitor in parallel with the output signal
The first method is often the simplest and most effective.
Using a resistor or ferrite gives the designer greater transient control and less impact on changes that occur in logic families over time. The advantage of using a control capacitor is that it can be easily removed when not needed. However, it must be remembered that capacitors increase the current of the RF signal source.
It's also a good idea to choose your active devices carefully. Not all pin-compatible semiconductor components are equivalent in terms of noise. Two devices with the same technical parameters, but made by different manufacturers, can differ significantly in the noise they create at the input and output pins, as well as at the power pins. This is especially true for highly integrated chips such as microprocessors and large application-specific applications. integrated circuits(ASIC). It's a good idea to evaluate components from different vendors whenever possible.
Finally, take another look at your design. Even if you are an experienced PCB designer and EMC expert, it is good to have someone who is knowledgeable about EMC analysis and familiar with PCB design. Let him critically examine your design.
Whose advice can you trust? Trust anyone whose recommendations clearly help you fulfill the four main rules. A little extra care during design can save a lot of time, money and effort that would be wasted trying to get an otherwise intractable product to work correctly.
Translation of the article:
Dr. Todd Hubing, Dr. Tom Van Doren
Designing for EMC: The TOP 4 GUIDELINES
Printed Circuit Design & Manufacture, June 2003
Dr. Todd Hubing, Professor Emeritus of Electrical Engineering and computer technology, twice awarded the prize “ Best Publications Symposium” of the International Symposium of the Institute of Electrical and Electronics Engineers.
Dr. Tom Van Doren, professor of electrical and computer engineering at the Electromagnetic Compatibility Laboratory at the University of Missouri-Rolla.
Profits in consumer electronics are tight, and manufacturers are struggling to maintain low cost products to maintain competitiveness. For this reason, they require developers to use low-cost printed circuit boards (PCBs) and components while maintaining the desired functionality of the devices. Manufacturers believe that ensuring electromagnetic compatibility (EMC) in PCB design and using components with high level EMC is a luxury they cannot afford.
Many believe that EMC problems can be solved at the end of the development cycle by additional components, suppressing electromagnetic interference. It is not always obvious that the cost of such corrections at the final stages of development will be many times higher than the cost of ensuring electromagnetic compatibility at the initial stages of design when creating a PCB. Thus, the desire to reduce the cost of materials and components will actually lead to a significant increase in the cost of the product.
To develop a printed circuit board with a low noise level and minimal sensitivity to interference, it is necessary, firstly, to properly organize the ground circuit, and secondly, to correctly layout the printed circuit board. For any PCB it is desirable to have a minimum ground impedance to ensure efficient flow of currents when interference occurs. On the other hand, it is a competent layout that is prerequisite creating a good PCB. Proper routing not only reduces the impedance of the conductors, but also avoids common impedance coupling.
High Frequency PCB: Digital Circuits and Noise
Digital integrated circuits(ICs) containing logic gates are a source of impulse noise due to delays when turning off the transistors. Each time a logic gate changes state, a short pulse of through current flows through the complementary transistors of the output stage. The inductance of the ground paths does not allow the current to change abruptly, which leads to a voltage surge.
To reduce the impact of such interference, all digital circuits must have a minimum ground impedance. Moreover, next to each logic chip a decoupling component must be installed to ensure that the flow path pulse current will not extend to the Vcc power supply.
Ground impedance can be reduced in several ways: by reducing the inductance of the conductive path, reducing the area of current loops, and reducing the length of the paths through which current flows. This can be achieved in part by decoupling components located near each logic chip.
Reducing the inductance of ground conductors
The inductance of a conductor is directly proportional to its length. Therefore, it is necessary to reduce the length of the tracks along which pulse currents flow. An additional reduction in inductance is also possible by increasing the width of the power traces. Unfortunately, inductance is inversely proportional to trace width, and this approach is not very effective. As a result, it is the length of the track that is the most important factor from the point of view of ensuring minimum inductance.
If we neglect mutual inductance, then the equivalent inductance of two identical parallel tracks will be half as much. In the case of four parallel tracks, the equivalent inductance will be four times less. However, there is a limit to using this approach. The fact is that if the tracks are close to each other, then the mutual inductance approaches the self-inductance, and the equivalent inductance does not decrease. However, if the traces are spaced at a distance twice their width, a 25% reduction in inductance can be achieved.
Thus, in high frequency circuit As many alternative parallel paths as possible should be provided for the flow of earth currents. If we increase the number of conductors infinitely, we will eventually arrive at a layer of continuous earth. Using a separate ground layer in multilayer boards allows you to solve a huge number of problems at once.
If we're talking about about a two-layer board, then an acceptable result can be achieved by implementing the ground in the form of a grid (Fig. 1). In this case, the best option would be when the ground path runs under each microcircuit along its entire length. It is allowed to use a vertical grid pitch equal to the length of the IC. Vertical and horizontal traces can be on opposite sides of the board, but must be connected at grid nodes using vias.
Rice. 1. The ground is made in the form of a grid
It turned out that if in a conventional double-sided printed circuit board with 15 microcircuits the ground is made in the form of a grid, then the ground noise is reduced tenfold. Therefore, all double-layer PCBs with digital chips should use this solution.
Reducing the area of current loops
Another method of reducing inductance is to reduce the area of current flow paths. A printed circuit board with a large open loop (Figure 2 a) is an effective noise generator. In addition, the circuit itself will also be sensitive to external magnetic fields.
Consider a power loop consisting of two identical parallel traces - the supply trace Vcc and the ground trace GND - in which the currents flow in opposite directions. Their total inductance (Lt) is calculated using formula 1:
Lt = 2 (L - M) (1)
where L is the inductance of each track, and M is the mutual inductance.
If the Vcc and ground traces are placed close together, the mutual inductance will be maximized and the effective inductance will be reduced by almost half. Ideally, on a PCB, the Vcc trace should run parallel to the ground trace. This reduces the area of the current loop and helps solve problems associated with noise generation and sensitivity to interference.
In Fig. 2a shows an unsuccessful printed circuit board layout, and Fig. 2 b shows an improved version. By reducing the loop area, it was possible to reduce the track length and increase mutual inductance, which made it possible to achieve lower emissions and susceptibility to interference.
Decoupling capacitors
In Fig. 3 and the Vcc and ground traces are located close to each other. However, the pulsed current path starting and ending at the power supply forms a large loop (green area in the figure) that can generate electromagnetic interference. If a ceramic decoupling capacitor Cc is placed near each IC, connected between Vcc and ground, it will act as a buffer element to provide power to the IC during the switching time, thereby reducing the current flow path.
Rice. 3. Decoupling capacitor
Ideally, the decoupling capacitor should be around 1 nF. Ceramic capacitors should be used as they are capable of delivering charge with very high high speed. High current discharge and low self-inductance make them perfect choice for power supply decoupling.
Impedance coupling in printed circuit boards
In Fig. Figure 4 shows an example of impedance coupling using common power and ground rails. In this circuit, an analog amplifier shares the power and ground rails with a logic gate. The track impedances are shown as lumped elements (Zg and Zs). On higher frequencies The impedances of the tracks increase many times over. This occurs not only due to an increase in the inductive component, but also due to an increase in resistance caused by the skin effect.
Rice. 4. Common impedance coupling
As we saw earlier, a voltage surge occurs whenever a logic gate is switched. Part of the ground impedance (Zg3) is common to both the amplifier and logic gate, so the amplifier will see this voltage pulse as noise in the power supply. This noise can be transferred to the amplifier circuit either directly through the power input or through the common impedance Zg3. As a result, noise will appear directly at the amplifier input. To reduce the total impedance coupling, you must either reduce the value of the total impedance or completely get rid of it.
Eliminating Total Impedance
Common impedance can be eliminated by connecting the power supply circuits of different circuits at the same point ("star"), as shown in Figure 5. To do this, it is necessary to group the circuits depending on their noise level and susceptibility to interference. Common buses can be used within each group, but power lines separate groups connect at one point. This connection is called hybrid. The second approach is to use separate power supplies for each group of circuits, which further improves the isolation between circuits.
Rice. 5. Connection at one point
December 11, 2016 at 5:48 pmLittle secrets of routing boards with operational and instrumentation amplifiers
- Internet of Things,
- Sound ,
- Electronics for Beginners
- Tutorial
When designing boards
Nothing comes so cheap
And not valued so highly
How to properly trace.
In the age of the Internet of things and the availability of printed circuit boards, and not only using LUT technology, their design is often carried out by people whose entire activity is related to digital technology.
Even when tracing is simple digital board There are unspoken rules that I always follow in my projects, and in the case of developing measuring devices with digital-analog circuit sections, this is simply necessary.
In this article, I want to draw novice designers to a number of elementary techniques that should be followed in order to obtain a stable operating circuit and reduce measurement error or minimize distortion. sound path. For clarity, the information is presented in the form of two examples.
Example number two. Tracing a simple op-amp circuit
Rice. 1. Op-amp amplifier circuit
Rice. 2. Two options for tracing the amplifier board to the op-amp
A small off-topic, not directly related to the topic of today’s article
I strongly advise you to use the same technique when supplying power to other types of microcircuits, especially ADCs, DACs and numerous power pins of microcontrollers. If you use built-in analog microcontroller modules - ADC, DAC, comparators, reference voltage sources, do not be lazy to look at the datasheet and see which blocking capacitors, in what quantity, and where should be installed. An decoupling circuit in the form of a filter or at least a resistance between the main digital power microcontroller and analog. It is better to place the analog ground as a separate polygon or screen layer, and connect it to the main ground at one point, in some cases it is useful through a filter
Circuit elements feedback should be located as close as possible to the non-inverting input, which minimizes the possibility of interference with the high-impedance input circuit.
Let's move on to a more serious and interesting case from the field of measurements, where tracing can be extremely important.
Example number one. Tracing a current consumption monitor on an instrumentation amplifier
Rice. 3. Current monitor circuit using instrumentation op-amp
The figure shows a diagram of a current consumption meter. The measuring element is the shunt resistance included in the power circuit. The load at which the current is measured is R load. The measured voltage is removed from the resistance R shunt and filtered using a symmetrical circuit on elements R1, R2, C1-C3. Chip U2 serves to supply the reference voltage. R4, C5 - output filter.
When tracing, of course, you must follow all the recommendations given above.
Rice. 4. Two options for routing the amplifier board on an instrumentation op-amp
Let's look at the shortcomings that the left diagram has:
- Since we have a differential input, it is necessary to make its two signal paths as symmetrical as possible. The signal line conductors must be of the same length and located close to each other. Ideally at the same distance from each other;
- The reference follower IC must be located as close as possible to the reference voltage input of the instrumentation amplifier.
Do not keep a loaded gun on the wall. One day it will definitely shoot and choose the most inconvenient moment for this.
