Development and description of a system of measuring channels to determine static and dynamic characteristics. ADC with push-pull integration. Methods for identifying and correcting DAC errors
Analog-to-digital converters (ADCs) are devices that receive analog signals and produce digital signals at the output, suitable for operation of computers and other digital devices. The conversion characteristic reflects the dependence of the output digital code from the input DC voltage. The transformation characteristic can be specified graphically, tabularly or analytically.
STATIC PARAMETERS
Intercode voltage– the point at which both adjacent code combinations are equally probable.
Quantization step– difference between adjacent values of intercode transition voltages.
Zero offset voltage – parallel shift of the transformation characteristic relative to the abscissa axis.
Conversion factor deviation– error at the end of the transformation characteristic.
ADC non-linearity– Deviation of the actual value of the input voltage at a given point from the actual value determined by the linearized conversion characteristic at the same point. Expressed as a number of quantization steps or relative to the maximum input voltage as a percentage.
Differential nonlinearity– deviation of actual quantization steps from their average value.
DYNAMIC PARAMETERS OF ADC.
1. Sampling frequency - the frequency at which sample values of the signal are generated, measured in the number of samples per second, or in hertz.
2. Conversion time – time from the ADC trigger pulse or from the time of analog change input signal until a stable output code appears. For some ADCs this value depends on the input signal, for others it is constant. When working without UVH, this value is the aperture time.
3. Frequency error of the transmission coefficient - the error in the formation of sample values when working with changing signals. Defined for a sinusoidal input signal. (For ADC K1107 PV2 8 bit, 80 MHz: P = 7 MHz at level 0.99).
4. Aperture time - the time during which uncertainty remains between the sample value and the time to which it refers. Consists of aperture shift and aperture uncertainty.
Depending on how the conversion process unfolds over time, ADCs are divided into:
1. Sequential
2. Parallel
3. Series - parallel.
SERIAL ADCs
ADC with step ramp voltage.
A positive voltage is supplied to the converter input. The counter is pre-set to zero, so the voltage at the DAC output is also 0. At the same time, logic 1 is set at the comparator output. The input of the 3I-NOT circuit receives pulses from the clock pulse generator. However, since log.0 is written to the R-S trigger, pulses do not pass to the counter input.
After the start pulse R-S trigger goes into a state with log.1 at the output and clock pulses begin to arrive at the counter input. The number recorded in the counter begins to increase and the voltage at the DAC output increases accordingly. At some point it is compared with the input voltage at the converter input, the comparator switches to log.0. and pulses stop arriving at the counter input. This signal from the comparator also arrives at the input of the RS trigger, switching it to the log.0 state at the output, which finally stops the conversion process. The resulting output code corresponds to the voltage at the low-order DAC output, or to the input analog signal with an accuracy of one. The process can then be repeated.
The minimum period of clock pulses can be found from the condition:
Cumin ≥ tcomp. + tdigit. + tDC + tRC, where:
tcomp – comparator response delay,
tdigits – counter delay,
tsap – DAC establishment time,
t RC – delay RC – chains.
Example. Let's calculate the conversion time of an ADC with 10 bits.
Elements used:
DAC – K572 PA1: number of bits N = 10, time to establish output voltage tdac = 5 ∙ 10 -6 sec. At Vop = 10V quantization step
EMP = 10/(2 10 –1) = 10 mV.
COMPARATOR – 521 CA3 - at dV = 3 mV tcomp = 100 nsec.
We choose the time constant RC equal to 0.5 ∙ 10 -6 sec.
tdigit = 0.05 ∙ 10 -6 sec,
Cumin ≥ 0.1 + 0.05 + 5. 0 + 0.5 = 5.65 µs.
Maximum input signal measurement time:
(2 10 – 1) ∙ 5.65 ∙ 10 – 6 sec = 6 msec, sampling frequency is 160 Hz.
Aperture time – 6 ms.
ADCs of this type are used with UVH, or for converting slowly changing signals. The ADC error is determined by the accuracy parameters of the DAC used.
A variety of this type of ADC is tracking ADCs carry out the transformation continuously. They use an up/down counter and a comparator determines the direction of counting. At Vin< Vцап счетчик считает вверх, в при Vвх >The VDC counter counts down. Thus, the voltage Vdac constantly tends to be equal to Vin. The maximum input tracking speed is: dVin/dt< ЕМР/ Тмин.
Successive approximation ADC.
The procedure for determining the output code is determined by the successive approximation register. At the beginning, log.0 is written to all bits of the register. The voltage at the DAC output is zero. Next, log.1 is written to the most significant bit of the register. If output voltage In this case, the DAC is still less than the input voltage (log. 1 is set at the comparator output, then the value of the logical level in this bit is stored. If the voltage at the DAC output is greater than Vin., then this bit is reset to zero and then log. 1 is written to the next digit. In this way, the values of all digits, including the least significant one, are determined. After this, a readiness signal is issued and the measurement cycle can be repeated.
This type of DAC has a speed advantage over the previous DAC, so it is the most widely used. Its conversion time is equal to Tmin ∙ N.
Tmin – the minimum value of the clock pulse repetition period is determined similarly to the previous DAC, N – the number of bits.
Example: the integrated ADC 1108 PV2 has all the elements on the chip: DAC, reference voltage source, successive approximation register, clock generator, comparator. N = 12, minimum conversion time - 2 µs.
DAC with time-pulse conversion (linear coding method).
An ADC of this type uses the conversion of the measured voltage into a time interval proportional to it, which is filled with pulses of a reference frequency. This time interval is formed by a sawtooth voltage generator (RVG) and a comparator. The number of pulses is considered a counter which determines the ADC output code.
The performance of such a circuit is higher than that of a DAC with a stepped sawtooth voltage, since it does not have a DAC and is determined by the performance of the comparator and counter. The comparator turn-off time is selected under the condition of the overexcitation that provides the necessary error in comparing the input signal and the sawtooth voltage.
To reduce errors, the reference frequency generator and the GPG must be mutually stable.
The ADC is described: N = 10, f etal = 100 MHz, t convert. = 10 µsec.
ADC with push-pull integration.
The disadvantage of the sequential ADCs discussed above is their relatively low noise immunity, which limits their resolution. An increase in the number of bits is associated with the use of high-precision DACs, which makes the production of such ADCs more expensive.
The principle of double integration in an ADC allows one to largely get rid of these shortcomings. The full cycle of its operation consists of two cycles. In the first, the input voltage is integrated using an analog integrator over a fixed time interval T0. This time interval is formed by a counter, the input of which receives pulses from a generator with a frequency fsch.
Interval T0 is equal to:
Т0 = Nmax ∙ tсч
Here tcount = 1/fc is the frequency period of the clock generator, Nmax is the maximum counter capacity, which determines the resolution of the ADC.
The charge on capacitor C will then be equal to:
In the second cycle, the capacitor is discharged from the reference voltage source Vref. The polarity of the reference voltage is opposite to the polarity of the input signal, so the voltage across capacitor C begins to decrease. The counter counts the generator pulses at this time clock frequency fcount, starting from the zero state. At the point in time when the comparator passes through zero, counting stops and the number is written to the output register. The charge q2 that discharged the capacitor is equal to.
Digital-to-analog converters have static and dynamic characteristics.
Static characteristics of the DAC
Main static characteristics DACs are:
· resolution;
· nonlinearity;
· differential nonlinearity;
· monotony;
· conversion factor;
· absolute full scale error;
· relative full scale error;
· zero offset;
absolute error
Resolution – this is the increment of U OUT when transforming adjacent values D j, i.e. differing by one least significant unit (EMP). This increment is the quantization step. For binary conversion codes, the nominal value of the quantization step is
h = U PS /(2 N – 1),
where U PN is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit capacity of the DAC. The higher the bit depth of the converter, the higher its resolution.
Full scale error – the relative difference between the real and ideal values of the conversion scale limit in the absence of a zero offset, i.e.
It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.
Zero offset error – the value of U OUT when the DAC input code equal to zero. It is an additive component of the total error. Typically stated in millivolts or as a percentage of full scale:
Nonlinearity – maximum deviation real characteristics transformation U OUT (D) from the optimal one (Fig. 5.2, line 2). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Nonlinearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristics shown in Fig. 5.2,
Differential nonlinearity – the maximum change (taking into account the sign) of the deviation of the actual transformation characteristic U OUT (D) from the optimal one when moving from one value of the input code to another adjacent value. Usually defined in relative units or in EMR. For the characteristics shown in Fig. 5.2,
Monotone conversion characteristics - increase (decrease) of the DAC output voltage (U OUT) with an increase (decrease) of the input code D. If the differential nonlinearity is greater than the relative quantization step h/U PN, then the converter characteristic is nonmonotonic.
The temperature instability of the DAC is characterized by temperature coefficients full scale errors and zero offset errors.
Full scale and zero offset errors can be corrected by calibration (tuning). Nonlinearity errors by simple means cannot be eliminated.
Dynamic characteristics of the DAC
TO dynamic characteristics am DACs include settling time and conversion time.
With a sequential increase in the values of the input digital signal D(t) from 0 to (2 N – 1) through the least significant digit, the output signal U OUT (t) forms a stepped curve. This dependence is usually called the DAC conversion characteristic. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (see Fig. 5.2), which corresponds to the ideal conversion characteristic. The actual transformation characteristic may differ significantly from the ideal one in terms of the size and shape of the steps, as well as their location on the coordinate plane. To quantify these differences, there is whole line parameters.
The dynamic parameters of the DAC are determined by the change in the output signal when abrupt change input code, usually from the value “all zeros” to “all ones” (Fig. 5.3).
Settling time
– time interval from the moment of betrayal
input code (Fig. 5.3, t = 0) until the last time the equality is satisfied:
|U OUT – U ПШ | = d/2,
with d/2 usually corresponding to EMP.
Slew rate – maximum speed changes in U OUT (t) during the transient process. Defined as the increment ratio D U OUT to the time Dt during which this increment occurred. Usually indicated in technical characteristics ah DAC with an output signal in the form of voltage. For digital-to-analog converters with current output, this parameter largely depends on the type of output op-amp.
For multiplying DACs with voltage output, the unity gain frequency and power bandwidth are often specified, which are mainly determined by the properties of the output amplifier.
Figure 5.4 shows two linearization methods, from which it follows that the linearization method for obtaining the minimum value of D l, shown in Fig. 5.4, b, allows you to reduce the error D l by half compared to the linearization method at boundary points (Fig. 5.4, a).
For digital-to-analog converters with n binary digits, in the ideal case (in the absence of conversion errors), the analog output U OUT corresponds to the input binary number in the following way:
U OUT = U OP (a 1 2 -1 + a 2 2 -2 +…+ a n 2 -n),
where U OP is the reference voltage of the DAC (from the built-in or external source).
Since ∑ 2 -i = 1 – 2 -n, then with all bits turned on, the output voltage of the DAC is equal to:
U OUT (a 1 …a n) = U OP (1 – 2 -n) = (U OP /2 n) (2 n – 1) = D (2 n – 1) = U PS,
where U PN is the full scale voltage.
Thus, when all bits are turned on, the output voltage digital-to-analog converter, which in this case forms U PN, differs from the value of the reference voltage (U OP) by the value of the least significant digit of the converter (D), defined as
D = U OP /2 n.
When any i-th bit is turned on, the output voltage of the DAC will be determined from the relationship:
U OUT /a i = U OP 2 -i .
A digital-to-analog converter converts the digital binary code Q 4 Q 3 Q 2 Q 1 into an analog value, usually voltage U OUT. or current I OUT. Each rank binary code has a certain weight of the i-th digit twice as large as the weight of the (i-1)-th. The operation of the DAC can be described by the following formula:
U OUT = e (Q 1 1 + Q 2 2 + Q 3 4 + Q 4 8 +…),
where e is the voltage corresponding to the weight of the least significant digit, Q i is the value of the i-th digit of the binary code (0 or 1).
For example, the number 1001 corresponds to:
U OUT = e (1· 1 + 0 · 2 + 0 · 4 + 1 · = 9 · e,
and the number 1100 corresponds
U OUT = e (0· 1 + 0 · 2 + 1 · 4 + 1 · = 12 · e.
Significant difficulties arise when reducing the random error when measuring a time-varying quantity. At the same time, to obtain best estimate of the measured value, a filtering procedure is applied. Depending on the type of transformations used, linear and nonlinear filtering are distinguished, where the implementation of individual procedures can be carried out both in hardware and software.
Filtering can be used not only to suppress interference induced on the input transmission circuits analog signal, and, if necessary, to limit the spectrum of the input signal and restore the spectrum of the output signal (this was already discussed earlier). If necessary, filters with a tunable cutoff frequency can be used.
Application automatic correction systematic errors can be considered as adapting the channel to its own state. Application of modern element base allows today to implement input circuits that adapt to the characteristics of the input signal, in particular to its dynamic range. For such adaptation, an input amplifier with controlled gain is required. If, based on the results of previous measurements, it was possible to establish that the dynamic range of the signal is small compared to the range of the ADC input signal, then the amplifier gain is increased until the dynamic range of the signal corresponds to the operating range of the ADC. In this way, it is possible to minimize the signal sampling error and, consequently, increase the accuracy of measurements. The change in the signal gain at the input is taken into account in software when processing the measurement results by a digital controller.
Conformity assessment criteria dynamic range signal and the operating range of the ADC will be discussed further; methods for adapting the input channel to the frequency properties of the input signal will also be considered.
2.4. Sample-and-hold devices
When collecting information and its subsequent conversion, it is often necessary to fix the value of an analog signal for a certain period of time. For this purpose, sampling and storage devices (SSDs) are used. Another name for such devices is analog storage devices (AMD). Their work is carried out in two modes. In the sampling (tracking) mode, they must repeat the input analog signal at their output, and in the storage mode, they must store and output to their output the last input voltage preceding the moment the device switches to this mode.
In the simplest case, when constructing a UVH, to carry out these operations we only need a capacitor WITH XP and key S(Fig. 2.12. A). When the switch is closed, the voltage on the capacitor and at the output of the UVH will repeat the input. When the key is opened, the voltage on the capacitor, the value of which will be equal to the input voltage at the moment the key is opened, will be stored on it and transmitted to the output of the UVH.
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Rice. 2.12. Functional diagram of UVH ( A) and time diagrams of its operation ( b)
It is obvious that when practical implementation The voltage level on the capacitor in storage mode will not remain constant (Fig. 2.12. b) due to its discharge by current to the load and discharge due to its own leakage currents. In order for the capacitor voltage to remain at an acceptable level for as long as possible at the output of the UVH, a repeater is installed on the op-amp ( D.A. 1 in Fig. 2.12. A). As you know, a repeater has a high input impedance. This “decouples” the capacitor circuit and the load circuit in resistance and significantly reduces the discharge of the capacitor through the load. To reduce your own leakage currents, you need to choose a capacitor with a high-quality dielectric. And of course, in order for the voltage on the capacitor to remain constant for as long as possible, it is necessary to take as large a capacitance as possible.
When transferring the UVH from storage mode to tracking mode, the voltage on the capacitor will not immediately reach the current input voltage level (Fig. 2.12. b). The time it takes for this to happen will be determined by the time it takes for the capacitor to charge - this time is called the acquisition time or sampling time. The capacitor will charge the faster, the greater its charge current. In order for this current not to be limited by the output resistance of the previous stage, a repeater is also installed at the input of the UVH at the op-amp ( D.A. 2 in Fig. 2.12. A). IN in this case The property that the repeater has a low output impedance is used. The capacitor will charge the faster the smaller its capacity. Thus, the conditions for choosing the capacitance value of the capacitor for optimal operation of the UVH in different modes are contradictory - the capacitance of the capacitor must be selected each time based on the specific requirements for the duration of its operating modes.
The input follower drives a capacitive load. Therefore, to build it, operational amplifiers are used that are stable at unity gain and a large capacitive load.
When using UVH in an ADC, the storage time, as a rule, is not much longer than the conversion time of the ADC. In this case, the capacitor value is selected in such a way as to obtain best time capture provided that the voltage drop during one conversion does not exceed the value of the least significant digit of the ADC.
Since dielectric losses in a storage capacitor are one of the sources of errors, it is best to choose capacitors with a dielectric made of polypropylene, polystyrene and Teflon. Mica and polycarbonate capacitors already have very mediocre characteristics. And you should not use ceramic capacitors at all.
The accuracy characteristics of the UVH include the zero offset voltage, which usually does not exceed 5 mV (if an op-amp with bipolar transistors at the entrance; op amp with field effect transistors at the input, have a more significant zero offset) and the drift of the fixed voltage at a given capacity of the storage capacitor (for different UVHs from 10-3 to 10-1 V/s is normalized at the capacitance WITH XP = 1,000 pF). The amount of drift can be reduced by increasing the capacitance WITH HR. However, this degrades the dynamic characteristics of the circuit.
The dynamic characteristics of the UVH include: sampling time, which shows how long, under the most unfavorable conditions, the process of charging a storage capacitor with a given tolerance level lasts; and aperture delay - the period between the moment the control voltage is removed and the actual locking of the key.
There are many integrated circuits sampling-storage, having good characteristics. A number of circuits include an internal storage capacitor and guarantee maximum time samples of tens or hundreds of nanoseconds with an accuracy of 0.01% for a signal of 10 V. The aperture delay value for popular UVHs does not exceed 100 ns. If higher performance is required, hybrid and modular UVHs can be used.
As an example of the practical construction of the UVH in Fig. 2.13 is given functional diagram BIS K1100SK2 (LF398). The circuit has a common negative feedback, covering the entire circuit - from the repeater output to operational amplifier D.A. 2 to the repeater input on the amplifier D.A. 1.
Dating" href="/text/category/datirovaniye/" rel="bookmark">dating the ADC reading when measuring a variable signal, in multi-channel measuring systems for simultaneous data collection from various sensors, eliminating high-frequency emissions in the DAC output signal when changing the code. These and other applications of UVC will be discussed in more detail in further material.
3. DIGITAL TO ANALOG CONVERTERS
3.1 General implementation methods
Digital-to-analog converters (DACs) are devices used to convert digital code into an analog signal in magnitude proportional to the value of the code.
DACs are widely used for coupling digital control systems with actuators and mechanisms that are controlled by the level of the analog signal, as components more complex analog-to-digital devices and converters.
In practice, DACs are mainly used for converting binary codes, so further discussion will only be about such DACs.
Any DAC is characterized, first of all, by its conversion function, which connects a change in the input value (digital code) with a change in the output value (voltage or current) Fig. 3.1.
Rice. 3.1. Conversion function (transfer characteristic) of DAC
Analytically, the DAC conversion function can be expressed as follows (for the case when the output signal is represented by voltage):
U OUT = ( U MAX / N MAX) N VX, where
U OUT – output voltage value corresponding to the digital code N VX supplied to the DAC inputs.
U MAX – maximum output voltage corresponding to the maximum code applied to the inputs N MAX.
Size TO DAC defined by the ratio U MAX/ N MAX is called the digital-to-analog conversion ratio. Its constancy for the entire range of changes in the arguments determines the proportionality of changes in the value of the output analog signal to the corresponding changes in the value of the input code. That is why, despite the stepwise nature of the characteristic associated with a discrete change in the input value (digital code), it is believed that DACs are linear converters.
If the value N The VX can be represented through the values of the weights of its bits, the DAC conversion function can be expressed as follows:
U OUT = DAC, where
i– digit number of the input code N VX;
A i – value i th digit (zero or one);
U i – weight i-th category;
n– number of bits of the input code (number of bits of the DAC).
This method of recording the conversion function largely reflects the operating principle of most DACs, which essentially consists of summing the shares of an analog output value (summing analog measures), each of which is proportional to the weight of the corresponding digit.
In general, according to the construction method, DACs are distinguished with a weighted summation of currents, with a weighted summation of voltages, and based on a code-controlled voltage divider.
When constructing a DAC based on a weighted summation of currents in accordance with the values of the bits of the input code N The VX signals from the current generators are summed and the output signal is represented by current. The construction of a four-bit DAC using this principle is illustrated in Fig. 3.2. The values of the generator currents are selected proportional to the weights of the bits of the binary code, i.e. if the current value of the smallest current generator corresponding to the least significant bit of the input code is equal to I, then the value of each next one must be twice as large as the previous one - 2 I, 4I, 8I. Every i th digit of the input code N VX controls i-th key S i. If i th digit is equal to one, then the corresponding switch is closed and then the generator current, whose current value is proportional to the weight of this i th category, participates in the formation of the output current of the converter. Thus, it turns out that the output current is IN VH.
Rice. 3.2. Construction of a DAC based on weighted summation of currents
N S 1, S 2 and S 4 in the diagram in Fig. 3.2 will be closed, and the key S 3 – open. Thus, currents equal to I, 2I and 8 I. In total they will form the output current IEXIT = 11I, i.e. the value of the output current I N VX = 11.
When constructing a DAC based on a weighted summation of voltages in accordance with the values of the bits of the input code N The I/O output signal of the DAC is formed from the values of the voltage generators and is represented by voltage. The construction of a four-bit DAC using this principle is illustrated in Fig. 3.3. The values of the voltage generators are set in accordance with the binary distribution law - proportional to the weights of the bits of the binary code ( E, 2E, 4E and 8 E). If i th digit of the input code N BX is equal to one, then the corresponding switch must be open, and a voltage generator whose voltage value is proportional to the weight of this i-th category, participates in the formation of the output voltage U converter OUT. Thus, it turns out that the output voltage is U DAC OUTPUT is proportional to input code size N VH.
Rice. 3.3. Construction of a DAC based on weighted summation of voltages
For example, if the input code value N BX is equal to eleven, i.e. in binary form it is represented as (1011), then the keys controlled by the corresponding bits S 1, S 2 and S 4 in the diagram in Fig. 3.3 will be open, and the key S 3 – closed. Thus, voltages equal to E, 2E and 8 E. In total they will form the output voltage U OUT = 11 I, i.e. the value of the output voltage U OUT will be proportional to the value of the input code N VX = 11.
In the latter case, the DAC is implemented as a code-controlled voltage divider (Fig. 3.4).
Rice. 3.4. Construction of a DAC based on a code-controlled voltage divider
The code-controlled divider consists of two arms. If the bit width of the implemented DAC is equal to n, then the number of resistors in each arm is 2 n. The resistance of each arm of the divider is changed using keys S. The keys are controlled by the output unitary code of the decoder DC, and the keys of one arm are controlled directly by it, while the others are controlled through inverters. The output code of the decoder contains a number of units equal to the value of the input code N VH. It is not difficult to understand that the division coefficient of the divider will always be proportional to the value of the input code N VH.
The last two methods are not widely used due to the practical difficulties of their implementation. For a DAC structure with weighted summation of voltages, it is impossible to implement voltage generators that would allow a short circuit at the output, as well as switches that do not have residual voltages in the closed state. In a DAC structure based on a code-controlled divider, each of the two divider arms consists of very large number resistors (2 n), includes the same number of keys for managing them and a large decoder. Therefore, with this approach, the implementation of the DAC turns out to be very cumbersome. Thus, the main structure used in practice is the current-weighted summation DAC structure.
3.2 DAC with weighted current summation
Let's consider the construction of a simple DAC with weighted summation of currents. In the simplest case, such a DAC consists of a resistive matrix and a set of switches (Fig. 3.5).
Rice. 3.5. Resistive matrix DAC implementations
The number of keys and the number of resistors in the matrix is equal to the number of bits n input code N VH. Resistor values are chosen proportional to the weights of the binary code, i.e. proportional to the values of the series 2i,i = 1… n. When a voltage source is connected to a common node of the matrix and the keys are closed, current will flow through each resistor. The current values of the resistors, thanks to the appropriate choice of their values, will be distributed according to the binary law, i.e., proportional to the weights of the bits of the binary code. When submitting an entry code N VX keys are switched on in accordance with the value of the corresponding bits of the input code. The key is closed if the corresponding bit is equal to one. In this case, in the current node, currents are summed up, proportional to the weights of these bits, and the magnitude of the current flowing from the node as a whole will be proportional to the value of the input code N VH.
In such a structure there are two output nodes. Depending on the value of the bits of the input code, the corresponding keys are connected to the node connected to the output of the device, or to another node, which is most often grounded. In this case, current flows constantly through each resistor of the matrix, regardless of the position of the switch, and the amount of current consumed from the reference voltage source is constant.
Rice. 3.6. Implementations of a DAC based on a resistive matrix and with switches
A common disadvantage of both structures considered is the large ratio between the smallest and largest values of the matrix resistors. At the same time, despite big difference resistor ratings, it is necessary to ensure the same absolute fitting error for both the largest and smallest resistor ratings. That is, the relative accuracy of fitting large resistors should be very high. In an integrated DAC design with a number of bits of more than ten, this is quite difficult to achieve.
Structures based on resistive materials are free from all these disadvantages. R- 2R matrices (Fig. 3.7).
Rice. 3.7. DAC based implementations R-2R resistive matrix
and with switch keys
You can verify that with this construction of the resistive matrix, the current in each subsequent parallel branch is two times less than in the previous one, i.e. their values are distributed according to a binary law. The presence in the matrix of only two resistor values, differing by a factor of two, makes it possible to quite simply adjust their values, without making high demands on the relative accuracy of the adjustment.
3.3 DAC parameters and errors
The system of electrical characteristics of DACs, reflecting the features of their construction and operation, combines more than a dozen parameters. Below are the main ones, recommended for inclusion in the regulatory and technical documentation as the most common and most fully describing the operation of the converter in static and dynamic modes.
1. Number of bits – number of bits of the input code.
2. Conversion coefficient - the ratio of the output signal increment to the input signal increment for linear function transformations.
3. Time to establish the output voltage or current - time interval from the moment given change code at the DAC input until the moment at which the output voltage or current finally enters a zone with a width equal to the weight of the least significant bit (LSB), symmetrically located relative to the steady-state value. In Fig. Figure 3.8 shows the transition function of the DAC, showing the change in the DAC output signal over time when the code changes. In addition to the time of establishment, it also characterizes some other dynamic parameters DAC - the amount of overshoot of the output signal, the degree of damping, the circular frequency of the settling process, etc. When determining the characteristics of a particular DAC, this characteristic is removed when changing the code from zero value by a code equal to half its maximum value.
4. Maximum conversion frequency – the highest sampling frequency at which the specified parameters comply with the established standards.
There are other parameters that characterize the performance of the DAC and the features of its functioning. These include: input voltage low and high level, output leakage current, consumption current, output voltage or current range, influence factor of instability of power supplies and others.
The most important parameters for a DAC are those that determine its accuracy characteristics, which are determined by errors normalized by magnitude.
Rice. 3.8. Determining the settling time of the DAC output signal
First of all, it is necessary to clearly distinguish static and dynamic errors DAC. Static errors are the errors that remain after the completion of all transient processes associated with changing the input code. Dynamic errors are determined by transient processes at the output of the DAC or its component components that arise as a result of a change in the input code.
The main types of static DAC errors are defined as follows.
Absolute conversion error at scale end point– deviation of the output voltage (current) value from the nominal value corresponding to the end point of the conversion function scale. For DACs operating with external source reference voltage is determined without taking into account the error introduced by this source. Measured in units of the least significant digit of the conversion.
Zero offset voltage at the output – the voltage at the output of the DAC with a zero input code. Measured in low order units. Determines the parallel shift of the actual transformation function and does not introduce nonlinearity. This is an additive error.
Conversion factor error(scale) – multiplicative error associated with the deviation of the slope of the transformation function from the required one.
DAC non-linearity– deviation of the actual transformation function from the specified straight line. The main requirement for a DAC from this point of view is the mandatory monotonicity of the characteristic, which determines the unambiguous correspondence between the output and input signal of the converter. Formally, the monotonicity requirement consists in the constancy of the characteristic sign of the derivative throughout the entire working area.
Nonlinearity errors in general case divided into two types - integral and differential.
Integral nonlinearity error– maximum deviation of the actual characteristic from the ideal one. In fact, this considers the averaged transformation function. This error is determined as a percentage of the final range of the output value. Integral nonlinearity arises due to various nonlinear effects that affect the operation of the converter as a whole. They are most clearly manifested in the integrated design of converters. For example, it may be associated with different heating levels in the LSI of some nonlinear resistances for different input codes.
Differential nonlinearity error– deviation of the actual characteristic from the ideal one for adjacent code values. These errors reflect non-monotonic deviations of the actual characteristics from the ideal ones. To characterize the entire transformation function, the local differential nonlinearity with the maximum absolute value is selected. Limits acceptable values differential nonlinearity are expressed in units of the weight of the least significant digit.
Let's consider the reasons for the appearance of differential errors and how they affect the DAC conversion function. Let's imagine that all the weights of the bits in the DAC are set perfectly accurately, except for the weight of the most significant bit.
If we consider the sequence of all code combinations for a binary code of a certain bit depth, then the patterns of binary code formation determine, among other things, that in code combinations corresponding to values from zero to half the full scale (from zero to half the maximum code value), the most significant bit is always is equal to zero, and in code combinations corresponding to values from half the scale to its full value, the most significant digit is always equal to one. Therefore, when applying codes corresponding to the first half of the input code value scale to the DAC, the weight of the most significant digit does not participate in the formation of the output signal, and when applying codes corresponding to the second half, it is constantly involved. But if the weight of this digit is specified with an error, then this error will also be reflected in the formation of the output signal. Then this will be reflected in the DAC conversion function, as shown in Fig. 3.9. A.
Rice. 3.9. Influence of reference error on the DAC conversion function
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From Fig. 3.9. A. it can be seen that for the first half of the input code values, the real DAC conversion function corresponds to the ideal one, and for the second half of the input code values, the real conversion function differs from the ideal one by the amount of error in setting the weight of the most significant bit. Minimizing the influence of this error on the DAC conversion function can be achieved by choosing a conversion scale factor that will reduce the error at the end point of the conversion scale to zero (Fig. 3.9. b). It is clear that the differential errors are distributed symmetrically relative to the middle of the scale. This determined another name for them - symmetrical type errors. At the same time, it is clear that the presence of such an error determines the non-monotonic behavior of the DAC conversion function.
In Fig. 3.10. A. It is shown how the real DAC conversion function will differ from the ideal one, provided that there are no errors in setting the weights of all digits except the digit preceding the most significant one. Rice. 3.10. b. shows the behavior of the transformation function if the scale component of the total error is selected (reduced to zero).
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Zero offset error and scale error are easily corrected at the DAC output. To do this, a constant offset is introduced into the output signal, compensating for the offset of the converter characteristic. The required conversion scale is established either by adjusting the gain set at the output of the amplifier converter, or by adjusting the value of the reference voltage if the DAC is a multiplying one.
Let's look at the main electrical characteristics DAC and ADC. They are divided into static, which specify the final accuracy of the conversion, and dynamic, which characterize the performance of this class of devices. The static characteristics of the converters are determined by the type of conversion characteristic, which establishes a correspondence between the values of the analog quantity and the digital code. Let's take a closer look at them.
The number of bits (b) is the number of bits of the code reflecting the original analog value, which can be generated at the output of the ADC or supplied to the input of the DAC. When using binary code, b refers to the binary logarithm of the maximum number of code combinations (quantization levels) at the ADC output or DAC input.
Absolute resolution - average values of the minimum change in the signal at the DAC output (α), or the minimum change in the input signal of the ADC (m), due to an increase or decrease in its code by one.
The absolute resolution value is a measure of all the main static characteristics of a given class of devices and is often denoted as EMP (low order unit), or simply MP (low order unit).
The absolute conversion error at the end point of the scale (δF s) is the deviation of the real maximum values of the input for the ADC (U IRN) and output for the DAC (U ORN) analog signals from the values corresponding to the end point of the ideal conversion characteristic (U IRNmax and U ORNmax). In relation to the ADC, the presence of δF s means that the maximum output code will be generated at the output of the device with the input signal (U input = U IRNmax – F S). By analogy for the DAC, we can say that when the maximum code is applied to the input, its output voltage will differ from U ORNmax by the value F S . Typically δF s is measured in EMP. In the technical literature, δF s is sometimes called the multiplicative error.
The zero offset voltage U 0 - for an ADC - is the voltage (U input 0) that must be applied to its input to obtain a zero output code. For a DAC, this is the voltage present at its output (U out0) when a zero code is applied to the input. The value of U 0 is usually expressed in EMP.
Nonlinearity (δL) is the deviation of the actual transformation characteristic from the specified linear one. Those. this is the difference between the actual voltage corresponding to the selected code value and the voltage that should correspond to this code in the case of an ideal conversion characteristic of the device. For a DAC, this voltage is measured relative to the centers of the steps of the specified characteristics. As a specified linear characteristic, either a straight line drawn through points 0, U max, or a straight line that ensures minimization of δL is used, for example, the standard deviation of all points of which from the real characteristic is minimal. The value of δL is measured in EMP (δL = δ’L/h) or percentage (L = 100 · ‘L D max), where δ’L - absolute value nonlinearity. The reference literature usually specifies the maximum possible value of δL .
Differential nonlinearity (δL D). This is the deviation of the actual quantization step δ’L D from its average value (h). The value of δ'L D is measured either in EMP [δL D = (δ'L D -h)/h], or as a percentage δL D = (δ'L D - h) 100/U max.
The magnitude of differential nonlinearity is clearly related to the concept of monotonicity of DAC and ADC characteristics. If |δL D | > 1EMP, then the increment of the output signal at a given point of the characteristic can be either positive or negative. In the latter case, the transformation characteristic ceases to be monotonic.
Figure 7.5. Dynamic characteristics of ADC and DAC
The dynamic properties of DACs and ADCs are usually characterized by the following parameters (Fig. 7.5):
1) maximum frequency conversion (f sma x) - the highest sampling frequency at which the specified parameters correspond to the established standards;
2) establishment time of the output signal (t set) - the interval from the moment of a given code change at the DAC input to the moment at which the output analog signal finally enters a zone of a given width, symmetrically located relative to the established value (Fig. 206). Typically the width of this zone is set to 1EMP. Time t mouth is counted from the moment the input signal reaches the value of half the logical differential.
|U out – U psh | =d/2
3) RATE OF INCREASE – maximum rate of change of U out (t) during the transient process. It is defined as the ratio of the increment ΔUout to the time t during which this increment occurred. Usually specified in the technical specifications of a DAC with a voltage output signal. For a DAC with a current output, this parameter largely depends on the type of output op-amp.
Most important point What characterizes both DACs and ADCs is the fact that their inputs or outputs are digital, meaning that the analog signal is sampled by level. Typically an N-bit word is represented as one of 2N possible states, so an N-bit DAC (with a fixed voltage reference) can only have 2N analog signal values, and an ADC can only output 2N different binary code values. Analog signals can be represented in the form of voltage or current.
The resolution of an ADC or DAC can be expressed in several different ways: LSB weight, ppm FS, millivolts (mV), etc. Different devices (even from the same chip manufacturer) are defined differently, so ADC and DAC users must be able to convert the different characteristics to properly compare devices. Some values of the least significant bit (LSB) are given in Table 1.
Table 1. Quantization: Least Significant Bit (LSB) value
| Resolution ability N | 2N | Full scale voltage 10V | ppm FS | %FS | dB FS |
| 2-bit | 4 | 2.5 V | 250000 | 25 | -12 |
| 4-bit | 16 | 625 mV | 62500 | 6.25 | -24 |
| 6-bit | 64 | 156 mV | 15625 | 1.56 | -36 |
| 8-bit | 256 | 39.1 mV | 3906 | 0.39 | -48 |
| 10-bit | 1024 | 9.77 mV (10 mV) | 977 | 0.098 | -60 |
| 12-bit | 4096 | 2.44 mV | 244 | 0.024 | -72 |
| 14-bit | 16384 | 610 µV | 61 | 0.0061 | -84 |
| 16-bit | 65536 | 153 µV | 15 | 0.0015 | -96 |
| 18-bit | 262144 | 38 µV | 4 | 0.0004 | -108 |
| 20-bit | 1048576 | 9.54 µV (10 µV) | 1 | 0.0001 | -120 |
| 22-bit | 4194304 | 2.38 µV | 0.24 | 0.000024 | -132 |
| 24-bit | 16777216 | 596 nV* | 0.06 | 0.000006 | -144 |
All other values can be calculated by multiplying by coefficients equal to powers of 2. Before looking at the features internal device ADC and DAC, it is necessary to discuss the expected performance and the most important parameters digital-to-analog and analog-to-digital converters. Let's look at the definition of errors and technical requirements requirements for analog-to-digital and digital-to-analog converters. This is very important for understanding the strengths and weaknesses
ADCs and DACs built according to different principles. The first data converters were intended for use in measurement and control applications, where the exact timing of the input signal conversion was usually not important. The data transfer speed in such systems was low. In these devices, the characteristics of analog-to-digital and digital-to-analog converters are important. DC
, and the characteristics associated with frame synchronization and AC characteristics do not matter.
Today, many, if not most, ADCs and DACs are used in audio, video and radio signal sampling and reconstruction systems, where their AC characteristics are decisive for the operation of the entire device, while the DC characteristics of the converters may not be important.
Figure 1 shows the ideal transfer function of a unipolar, three-bit digital-to-analog converter. In it, both the input and output signals are quantized, so the transfer function graph contains eight separate points. Regardless of how this function is approximated, it is important to remember that the actual transmission characteristic of a digital-to-analog converter is not a continuous line, but a number of discrete points.
Figure 2 shows the transfer function of a three-bit ideal unsigned analog-to-digital converter. Note that the analog signal at the ADC input is not quantized, but its output is the result of quantizing that signal. The transfer characteristic of an analog-to-digital converter consists of eight horizontal lines, but when analyzing the offset, gain and linearity of the ADC, we will consider the line connecting the midpoints of these segments.
Figure 2. Transfer function of an ideal 3-bit ADC.
In both cases discussed, the full digital scale (all "1s") corresponds to the full analog scale, which coincides with the reference voltage or a voltage dependent on it. Therefore, a digital code represents a normalized relationship between an analog signal and a reference voltage.
The transition of an ideal analog-to-digital converter to the next digital code occurs from a voltage equal to half the least significant digit to a voltage less than half the least significant digit of the full scale voltage. Since the analog signal at the ADC input can take any value, and the output digital signal is discrete signal, then an error occurs between the actual analog input signal and the corresponding digital output value. This error can reach half the least significant digit. This effect is known as quantization error or transformation uncertainty. In devices that use signals alternating current,this quantization error results in quantization noise.
The examples shown in Figures 1 and 2 show the transient characteristics of unsigned converters operating with a signal of only one polarity. This is the simplest type of converter, but bipolar converters are more useful in real applications.
There are two types of bipolar converters currently in use. The simpler of them is a conventional unipolar converter, the input of which is supplied with an analog signal with a constant component. This component introduces an offset of the input signal by an amount corresponding to the most significant bit (MSB) unit. Many converters can switch this voltage or current to allow the converter to be used in either unipolar or bipolar mode.
Another, more complex type of converter is known as a signed ADC and in addition to N information bits there is an additional bit that shows the sign of the analog signal. Sign analog-to-digital converters are used quite rarely, and are used mainly as part of digital voltmeters.
There are four types of DC errors in ADCs and DACs: offset error, gain error, and two types of linearity errors. The offset and gain errors of ADCs and DACs are similar to those of conventional amplifiers. Figure 3 shows the conversion of bipolar input signals (although the offset error and zero error, which are identical in amplifiers and unipolar ADCs and DACs, are different in bipolar converters and should be taken into account).
Figure 3: Converter Zero Offset Accuracy and Gain Accuracy
The transfer characteristic of both DAC and ADC can be expressed as D = K + GA, where D is a digital code, A is an analog signal, K and G are constants. In a unipolar converter, the coefficient K is equal to zero; in a bipolar converter with a bias, it is equal to one of the most significant digits. The bias error of the converter is the amount by which the actual value of the gain K differs from the ideal value. Gain error is the amount by which the gain G differs from the ideal value.
In general, the gain error can be expressed as the difference between two coefficients, expressed as a percentage. This difference can be considered as the contribution of the gain error (in mV or LSB values) to the total error at the maximum input signal value. Typically the user is given the opportunity to minimize these errors. Note that the amplifier first adjusts the offset when the input signal is zero, and then adjusts the gain when the input signal is close to the maximum value. The algorithm for tuning bipolar converters is more complex.
The integral nonlinearity of the DAC and ADC is similar to the nonlinearity of the amplifier and is defined as the maximum deviation of the actual transmission characteristic of the converter from a straight line. In general, it is expressed as a percentage of full scale (but can be represented in LSB values). There are two common methods approximation of transmission characteristics: end point method and best straight line method (see Figure 4).
Figure 4. METHOD FOR MEASURING TOTAL LINEARITY ERROR
When using the end point method, the deviation of an arbitrary characteristic point (after gain correction) from a straight line drawn from the origin is measured. Thus, at Analog Devices, Inc. measure the values of the integral nonlinearity of converters used in measurement and control tasks (since the magnitude of the error depends on the deviation from the ideal characteristic, and not on an arbitrary “best approximation”).
The best straight line method provides a more adequate prediction of distortion in applications dealing with AC signals. It is less sensitive to nonlinearities in technical characteristics. According to the best approximation method, a straight line is drawn through the transmission characteristic of the device using standard methods curve interpolation. After this, the maximum deviation is measured from the constructed straight line. Typically, integral nonlinearity measured in this way accounts for only 50% of the nonlinearity estimated by the end-point method. This makes the method preferable when specifying impressive technical characteristics in a specification, but less useful for analysis real values errors. For AC applications, it is better to determine harmonic distortion than DC nonlinearity, so the best straight line method is rarely needed to determine converter nonlinearity.
Another type of converter nonlinearity is differential nonlinearity (DNL). It is associated with the nonlinearity of the code transitions of the converter. Ideally, a change of one unit in the least significant bit of the digital code exactly corresponds to a change of one unit in the least significant bit of the analog signal. In a DAC, changing one least significant bit of the digital code should cause a change in the signal at the analog output exactly corresponding to the value of the least significant bit. At the same time, in the ADC when moving from one digital level the next, the value of the signal at the analog input must change exactly by the value corresponding to the least significant digit of the digital scale.
Where the change in the analog signal corresponding to a change in the least significant bit of the digital code is greater or less than this value, we speak of a differential nonlinear (DNL) error. The DNL error of a converter is usually defined as the maximum value of differential nonlinearity detected at any transition.
If the DAC's differential nonlinearity is less than –1 LSB at any transition (see Figure 2.12), the DAC is said to be nonmonotonic, and its transmission response contains one or more local maxima or minima. Differential nonlinearity greater than +1 LSB does not cause monotonicity violation, but is also undesirable. In many DAC applications (especially closed-loop systems where non-monotonicity can change negative feedback to positive feedback), DAC monotonicity is very important. Often the monotonicity of a DAC is explicitly stated in the datasheet, although if the differential nonlinearity is guaranteed to be less than the least significant bit (i.e. |DNL| . 1LSB), the device will be monotonic even if it is not explicitly stated.
It is possible for an ADC to be non-monotonic, but the most common manifestation of DNL in an ADC is missing codes. (see Fig. 2.13). Missing codes (or non-monotonicity) in an ADC are just as undesirable as non-monotonicity in a DAC. Again, this occurs when DNL > 1 LSB.
Figure 5. Non-ideal 3-bit DAC transfer function
Figure 6. Non-ideal 3-bit DAC transfer function
Determining missing codes is more difficult than determining non-monotonicity. All ADCs are characterized by some transition noise, illustrated in Figure 2.14 (think of this noise as the last digit of a digital voltmeter flickering between adjacent values). As resolution increases, the range of the input signal corresponding to the transition noise level can reach or even exceed the signal value corresponding to the least significant one. In this case, especially in combination with a negative DNL error, it may happen that there are some (or even all) codes where transition noise is present throughout the entire range of input signal values. Thus, there may be some codes for which there is no input signal value at which that code is guaranteed to appear in the output, although there may be some range of input signal at which the code will sometimes appear.
Figure 7. Combined effects of code transition noise and differential nonlinearity (DNL)
For a low-resolution ADC, the no-missing condition can be defined as a combination of transition noise and differential nonlinearity that would guarantee some level (say, 0.2 LSB) of noise-free code for all codes. However, it is not possible to achieve the high resolution of today's sigma-delta ADCs, or even the lower resolution of a wide-bandwidth ADC. In these cases, the manufacturer must determine noise levels and resolution in some other way. It is not so important which method is used, but the specification should clearly define the method used and the expected characteristics.
Literature:
- Analod-Digital Conversion, Walt Kester editor, Analog Devices, 2004. - 1138 p.
- Mixed-Signal and DSP Design Techniques ISBN_0750676116, Walt Kester editor, Analog Devices, 2004. - 424 p.
- High Speed System Application, Walt Kester editor, Analog Devices, 2006. - 360 p.
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