Will artificial neural networks replace conventional processors? Will neural mobile processors become a new milestone in the development of artificial intelligence technology?
Chinese company Huawei announced Kirin 970 - the first chipset to have a dedicated neural processor(NPU). Following the Chinese, Apple showed its A11 Bionic for iPhone models 8, 8 Plus and X. This chip, among other things, supports Neural Engine technology, which, according to company representatives, is “specially designed for machine learning" Quite recently, Qualcomm introduced its Snapdragon 845 chip, which can transfer tasks related to artificial intelligence to specific cores. There is no particular difference in the approaches of the companies. It all depends on available to developers core control levels and chip energy efficiency.
But are the new chips really significantly different from existing analogues on the market, and if so, what is their difference? The answer to this can be given by the term often found in reports on artificial intelligence - “heterogeneous computing”. It applies to processors that use specialized system features to improve performance or reduce power consumption. This approach has already been repeatedly implemented in previous generations of chips. New mobile processors they simply use this concept with some variations.
Natural development?
IN recent generations processors actively use ARM Big .Little technology. It combines slow, energy-efficient cores with more productive ones that have high energy consumption. The idea was to reduce the amount of energy to increase the autonomy of the devices. Last year, neural chips took another step in this direction, adding a separate element for processing tasks artificial intelligence, or, in the case of , using separate low-power cores for this task.
Apple's A11 Bionic mobile processor uses Neural Engine in combination with a graphics chip to speed up Face ID, Animoji, and speed up some non-native apps. When the user runs these processes on new iPhone, the chip includes a Neural Engine to process the wearer's face or project his facial expressions onto an animated picture.
The NPU takes over the functions of scanning and translating words in images obtained from using Microsoft Translator. However, for now the program is the only third party application, working with adapted Chinese manufacturer technology. According to Huawei, new technology HiAI accelerates most elements of the chipset and is capable of performing a much wider range of tasks than other NPUs.
New Horizons
When considered separately, the technology makes it possible to carry out, with no less efficiency, directly on the device those tasks that were previously processed using third-party cloud solutions. With the help of new components, a phone equipped with such chips will be able to perform more action simultaneously. This will affect many aspects of the device’s operation, from reducing the time for translations to searching for photos using internal hashtags. Also transferring the execution of such processes directly to the smartphone instead of using cloud solutions will have a positive impact on security and privacy, reducing the chances of hackers getting hold of user data.
One more important point New chips are power consumption, because energy is a valuable resource that requires reasonable distribution, especially when it comes to repetitive tasks. Graphics chips like to use up battery reserves very quickly, so offloading their processes to a DSP might be a good solution.
In fact, mobile processors themselves cannot independently make decisions about which cores need to be used when performing certain tasks. This depends on developers and equipment manufacturers using third-party supported libraries for this. , and actively integrate solutions such as TensorFlow Lite and Facebook Caffe2. Qualcomm also supports the new Open Neural Networks Exchange (ONNX), and Apple recently added interoperability for many new machine learning models in its Core ML framework.
Alas, the new mobile processors do not yet provide any special advantages. Manufacturers are already measured by their own test results and benchmarks. But without close integration with the environment modern user In reality, these indicators have little meaning. The technology itself is at a very early stage of development, and the developers using it are still few and scattered.
In any case, every new technology is a win for the user, be it increased productivity or improved energy efficiency. Manufacturers are serious about investing time and money in the development of neural chips, which means that future mobile processors will be able to offer a much wider list of tasks that will involve artificial intelligence.
IBM Corporation has overcome the next step in creating a chip for future supercomputers - a neural chip that works on the principle of human brain. The peculiarity of such a chip is that it is capable of self-learning, and also consumes hundreds of thousands of times less energy than conventional microprocessors. The new chip can already analyze visual information, which is confirmed by the test results.
Majority modern computers arranged according to the principle of von Neumann architecture. It is based on the joint storage of data and commands, while outwardly they are indistinguishable: the same information can become data, a command or an address, depending on how it is accessed. It is precisely this principle of operation of the von Neumann architecture that created its significant drawback - the so-called bottleneck (limitation bandwidth between processor and memory). The processor is constantly forced to wait for the necessary data, because program memory and data memory cannot be accessed at the same time: after all, they are stored on the same bus.
This problem was solved by the American programmer Howard Aiken, the author of Harvard architecture. It differs from the von Neumann architecture in that the data and instruction lines are physically separated, allowing the processor to simultaneously read instructions and access data, improving the speed of the computer. Despite this, at the end of the 1930s, at the competition for the development of a computer for naval artillery, announced by the US government, the von Neumann architecture won due to ease of implementation.
Later it became possible creation hybrid systems, combining the advantages of both architectures. However, with the development of programming, the minds of scientists began to be occupied by the idea of creating artificial neural systems: processors connected and interacting with each other, operating on the principle of functioning of the nerve cells of a living organism. The peculiarity of such systems is that they are not programmed, but trained.
The concept of an artificial neural network arose when studying the functioning of biological neural networks - a set of interconnected nervous system neurons that perform specific physiological functions. Each neuron is connected to a huge amount others, the place where neurons contact each other is called a synapse, which serves to transmit nerve impulses between cells.
The pioneers in the creation of artificial neural networks were Americans Warren McCulloch and Walter Pitts. In the early 1940s, scientists invented a model of the brain that simplistically viewed neurons as operating devices. binary numbers. The network of electronic “neurons” they invented could theoretically perform numerical or logical operations of any complexity. Fundamentally new theoretical foundations for such a model of the brain laid the basis for the subsequent development of neurotechnologies, and next step didn't keep me waiting.
Already in 1949, Donald Hebb proposed the first working algorithm for training artificial neural systems, and in 1958, Frank Rosenblatt created the first neurocomputer “Mark-1”. This computer was built on the basis of a perceptron, a neural network developed by Rosenblatt three years earlier.
One of the most promising areas for developing fundamentally new architectures computing systems is closely related to the creation of a new generation of computers based on the principles of information processing embedded in artificial neural networks(NS). The first practical work on artificial neural networks and neurocomputers began back in the 40s and 50s. A neural network is usually understood as a set of elementary information converters, called “neurons,” which are connected in a certain way to each other by information exchange channels “synaptic connections.”
Neuron, in essence, is an elementary processor characterized by input and output states, a transfer function (activation function) and local memory. The states of neurons change during operation and constitute the short-term memory of the neural network. Each neuron calculates the weighted sum of signals arriving at it via synapses and performs a nonlinear transformation on it. When sent across synapses, signals are multiplied by a certain weighting factor. The distribution of weighting coefficients contains information stored in associative memory NS. The main element of network design is its training. When training and retraining a neural network, its weighting coefficients change. However, they remain constant during the functioning of the neural network, forming long-term memory.
N 
C can consist of one layer, two layers, three and more, however, as a rule, to solve practical problems more than three layers in a neural network are not required.
The number of NN inputs determines the dimension of hyperspace, in which input signals can be represented by points or hyperregions of closely spaced points. The number of neurons in a network layer determines the number of hyperplanes in hyperspace. Calculating weighted sums and performing a nonlinear transformation make it possible to determine on which side of a particular hyperplane the input signal point is located in hyperspace.
Let's take the classic problem of pattern recognition: determining whether a point belongs to one of two classes. This problem is naturally solved using a single neuron. It will allow the hyperspace to be divided into two non-intersecting and non-nested hyperregions. In reality, input signals in problems solved using neural networks form highly nested or intersecting areas in hyperspace, which cannot be separated using a single neuron. This can only be done by drawing a nonlinear hypersurface between the regions. It can be described using an nth order polynomial. However, the power function is too slow to calculate and is therefore very inconvenient for computer technology. An alternative option is to approximate the hypersurface with linear hyperplanes. It is clear that the accuracy of the approximation depends on the number of hyperplanes used, which, in turn, depends on the number of neurons in the network. Hence the need arises for hardware implementation of as many neurons as possible in the network. The number of neurons in one layer of the network determines its resolution. A single-layer neural network cannot separate linearly dependent images. Therefore, it is important to be able to implement multilayer neural networks in hardware.
AND 
artificial neural networks
have amazing properties. They do not require detailed software development and open up the possibility of solving problems for which there are no theoretical models or heuristic rules that determine the solution algorithm. Such networks have the ability to adapt to changes in operating conditions, including the emergence of previously unforeseen factors. By their nature, NSs are systems with very high level parallelism.
IN neurocomputers the principles of information processing carried out in real neural networks are used. These fundamentally new computing tools with an unconventional architecture allow for high-performance processing of large-scale information arrays. Unlike traditional computing systems, neural network computers, similar to neural networks, make it possible to process with greater speed information flows discrete and continuous signals, contain simple computational elements and with a high degree of reliability allow you to solve information tasks data processing, while ensuring a mode of self-reconstruction of the computing environment depending on the decisions received.
Generally speaking, the term “Neurocomputer” currently means a fairly wide class of computers. This happens for the simple reason that formally, any hardware implementation of a neural network algorithm can be considered a neurocomputer, from a simple model of a biological neuron to a character recognition system or moving targets. Neurocomputers are not computers in the conventional sense of the word. Currently, technology has not yet reached the level of development at which one could talk about a neurocomputer general purpose(which would also be artificial intelligence). Systems with fixed values weighting coefficients are generally the most highly specialized of the neural network family. Learning networks are more flexible to the variety of problems they solve. Thus, the construction of a neurocomputer is each time the broadest field for research activities in the field of hardware implementation of almost all elements of the neural network.
At the beginning of the 21st century, unlike the 40-50s of the last century, there is an objective practical need to learn how to make neurocomputers, i.e. it is necessary to implement in hardware quite a lot of parallel operating neurons, with millions of fixed or parallel adaptively modified connections-synapses, with several fully connected layers of neurons. At the same time, integrated electronics technology is close to exhausting its physical capabilities. The geometric dimensions of transistors can no longer be physically reduced: with technologically achievable sizes of the order of 1 micron or less, physical phenomena appear that are imperceptible at large sizes active elements- quantum size effects begin to have a strong effect. Transistors stop working as transistors.
For the hardware implementation of the NN, a new storage medium is required. Such a new information carrier could be light, which will dramatically increase computational performance by several orders of magnitude.
The only technology for hardware implementation of neural networks that can replace optics and optoelectronics in the future is nanotechnology, capable of providing not only the physically maximum possible degree of integration of submolecular quantum elements with the physically maximum possible speed, but also the three-dimensional architecture so necessary for the hardware implementation of the neural network.
For a long time, it was believed that neurocomputers are effective for solving the so-called non-formalizable and poorly formalizable problems associated with the need to include the learning process using real experimental material in the algorithm for solving the problem. First of all, such problems included the task of approximating a particular form of functions that take a discrete set of values, i.e. pattern recognition problem.
Currently, a class of problems is being added to this class of problems, which sometimes do not require training on experimental material, but are well represented in a neural network logical basis. These include tasks with pronounced natural parallelism of signal processing, image processing, etc.. Confirmation of the point of view that in the future neurocomputers will be more efficient than other architectures can, in particular, be a sharp expansion in last years class of general mathematical problems solved in a neural network logical basis. These, in addition to those listed above, include problems solving linear and nonlinear algebraic equations and high-dimensional inequalities; nonlinear systems differential equations; partial differential equations; optimization problems and other problems.
A neural network is usually understood as a set of elementary information converters called “neurons”, which in a certain way connected to each other by information exchange channels - “synaptic connections”.A neuron is essentially an elementary processor characterized by an input and output state, a transfer function (activation function) and local memory.
Rice. 8.1.
The states of neurons change during operation and constitute the short-term memory of the neural network. Each neuron calculates the weighted sum of signals arriving at it via synapses and performs a nonlinear transformation on it. When sent across synapses, signals are multiplied by a certain weighting factor. The distribution of weight coefficients contains information stored in the associative memory of the neural network. The main element of network design is its training. When training and retraining a neural network, its weighting coefficients change. However, they remain constant during the functioning of the neural network, forming long-term memory.
The NS can consist of one layer, two, three or more layers, however, as a rule, to solve practical problems more than three layers in the NS are not required.
The number of NS inputs determines the dimension hyperspace, in which input signals can be represented by points or hyperregions of closely spaced points. The number of neurons in the network layer determines the number hyperplanes V hyperspace. Calculating weighted sums and performing a nonlinear transformation make it possible to determine on which side of a particular hyperplane the input signal point is located in hyperspace.
Rice. 8.2.
Let's take the classic problem of pattern recognition: determining whether a point belongs to one of two classes. This problem is naturally solved using a single neuron. It will allow you to divide hyperspace into two disjoint and non-nested hyperdomains. Input signals in problems solved using neural networks, they form in hyperspace highly nested or overlapping regions that cannot be separated using a single neuron. This can only be done by drawing a nonlinear hypersurface between the regions. It can be described using an nth order polynomial. However, the power function is calculated too slowly and is therefore very inconvenient for computing. Alternative option is the approximation of the hypersurface by linear hyperplanes. It is clear that the accuracy of the approximation depends on the number of used hyperplanes, which, in turn, depends on the number of neurons in the network. Hence the need arises for hardware implementation of as many neurons as possible in the network. The number of neurons in one layer of the network determines its resolution. A single-layer neural network cannot separate linearly dependent images. Therefore, it is important to be able to implement multilayer neural networks in hardware.
Rice. 8.3.
Artificial neural networks have amazing properties. They do not require detailed development software and open up possibilities for solving problems for which there are no theoretical models or heuristic rules that determine the solution algorithm. Such networks have the ability to adapt to changes in operating conditions, including the emergence of previously unforeseen factors. By their nature, NNs are systems with a very high level of parallelism.
Neurocomputers use the principles of information processing carried out in real neural networks. These fundamentally new computing tools with an unconventional architecture allow for high-performance processing of large-scale information arrays. Unlike traditional computing systems, neural network computers, similar to neural networks, make it possible to process information flows of discrete and continuous signals with greater speed, contain simple computational elements and with a high degree of reliability allow solving information problems of data processing, while providing a mode of self-reconstruction of the computing environment depending on the solutions obtained.
Generally speaking, the term “neural computer” currently means a fairly wide class of computers. This happens for the simple reason that formally any hardware implementation can be considered a neurocomputer. neural network algorithm, from a simple biological neuron model to a character or moving target recognition system. Neurocomputers are not computers in the conventional sense of the word. Currently, technology has not yet reached the level of development at which one could talk about a general-purpose neurocomputer (which would also be artificial intelligence). Systems with fixed values of weighting coefficients are generally the most highly specialized of the neural network family. Learning networks are more adapted to the variety of problems being solved. Learning networks are more flexible and capable of solving a variety of problems. Thus, the construction of a neurocomputer is each time the broadest field for research activities in the field of hardware implementation of almost all elements of the neural network.
At the beginning of the 21st century, unlike the 40-50s of the last century, there is an objective practical need to learn how to create neurocomputers, i.e. it is necessary to implement in hardware quite a lot of parallel operating neurons, with millions of fixed or parallel adaptively modified connections-synapses, with several fully connected layers of neurons.
At the same time, the physical capabilities of integrated electronics technology are not limitless. The geometric dimensions of transistors can no longer be physically reduced: with technologically achievable sizes of the order of 1 micron or less, physical phenomena appear that are invisible with large sizes of active elements - quantum size effects begin to have a strong effect. Transistors stop working as transistors.
For the hardware implementation of the NN, a new storage medium is required. Such a new information carrier could be light, which would allow one to sharply, by several orders of magnitude, increase performance calculations.
The only technology for hardware implementation of NS that can replace optics and optoelectronics in the future is nanotechnology, which can provide not only the physically maximum possible degree of integration of submolecular quantum elements with the physically maximum possible speed, but also the three-dimensional architecture so necessary for hardware implementation of NS.
For a long time it was believed that neurocomputers are effective in solving the so-called unformalizable and poorly formalizable tasks related to the need to include the learning process using real experimental material in the algorithm for solving the problem. First of all, such problems included the task of approximating a particular form of functions that take a discrete set of values, i.e., the problem of pattern recognition.
Currently, a class of problems is being added to this class of problems, which sometimes do not require training on experimental material, but are well represented in a neural network logical basis. These include tasks with pronounced natural parallelism in signal processing, image processing, etc. The point of view that in the future neurocomputers will be more efficient than other architectures can be confirmed, in particular, by the sharp expansion in recent years of the class of general mathematical problems solved in neural network logical basis. These, in addition to those listed above, include problems of solving linear and nonlinear algebraic equations and high-dimensional inequalities; systems of nonlinear differential equations; partial differential equations; optimization problems and other problems.
10/13/2017, Fri, 15:28, Moscow time, Text: Vladimir Bakhur
New flagship smartphone Huawei Mate The bezel-less 10 Pro will feature the latest Kirin 970 neural processor, dual optics from Leica, Android 8.0 Oreo and a smart pen. And not only.
Huawei has learned to pleasantly surprise
Blogger and journalist Evan Blass(Evan Blass), known for the high degree of confirmation of the insider information he publishes mobile gadgets, posted on his social page Twitter networks a number of new renders Huawei smartphone Mate 10 Pro.
A number of characteristics of the Huawei Mate 10 Pro smartphone, but it was from the latest publications of Evan Blas that it became known that new flagship will support a stylus with spatial position sensors, allowing you to write on paper with wireless transmission notes into a smartphone.
The announcement of the Mate 10 Pro family of smartphones is planned by Huawei on Monday, October 16, at 14:00 Moscow time. This is confirmed by the planned live broadcast of the HUAWEI Mate 10 Keynote Live presentation on YouTube from Munich with the participation of Huawei CEO Richard Yu.
The Bluetooth smart pen expected to come with the Mate 10 Pro looks similar to the stylus included in the Moleskine Smart Writing Set.
Technical details
Huawei Mate 10 Pro smartphone, which received working name Blanc ("regular" Mate 10 has working title Alps), will be one of the first gadgets on the market equipped with a mobile phone for the first time Huawei processor Hisilicon Kirin 970 with integrated artificial intelligence (AI) coprocessor.
Appearance of the Huawei Mate 10 Pro smartphone
The Kirin 970 mobile chip is an 8-core 64-bit processor based on four ARM Cortex-A73 cores with clock frequency 2.4 GHz and 4 ARM Cortex-A53 cores with clock speeds up to 1.8 GHz. The chip is equipped with integrated 12-core next-generation Mali-G72 MP12 graphics and a number of auxiliary coprocessors to accelerate specific computing tasks.
Key components of the Kirin 970 mobile processor
The chip contains 5.5 billion transistors placed on a 1 square meter chip. cm, and is produced at TSMC production facilities in compliance with the most precise 10 nm standards to date technological process FinFET.
New flagship processor Kirin 970 is a " mobile platform for solving AI problems.” It includes a so-called neural processing unit (NPU, Neural Processing Unit, NPU) for high-speed processing of artificial intelligence tasks with minimal energy consumption, providing, according to Huawei, 25x better performance and 50x higher efficiency than predecessors.
Kirin 970 also integrates cellular modem 4.5G with LTE support Category 18, 5CC, 4x4MIMO and 256QAM aggregations, which the company claims provides download speeds of up to 1.2 Gbps.
The chip supports simultaneous operation of two SIM cards in LTE mode, however, the Huawei Mate 10 Pro smartphone is expected to be presented as a Hybrid version Dual SIM(Nano-SIM, dual stand-by, one of the slots is combined with a microSD card reader for cards with a capacity of up to 256 GB), and in a version with one slot for a Nano-SIM card.
Kirin 970 provides hardware 4K video decoding up to 60fps and 4K video encoding up to 30fps with H.264 and H.265 codecs, and support color space HDR10. In addition, Kirin 970 supports up to 4 channels random access memory LPDDR4X 1866 MHz, equipped with built-in 32-bit/384 kHz DAC, Huawei sensor i7 new generation and support for dual cameras.
The Huawei Mate 10 Pro smartphone is expected to feature a large 5.99-inch display. AMOLED matrix with a resolution of 1440x2880 pixels, an aspect ratio of 18:9 and a sharpness of 546 pixels per inch. The thickness of the smartphone is only 7.5 mm, while it has protection according to the IP68 standard, which means 30 minutes of immersion of the device in water to a depth of 1.5 meters.
Main double Camera Mate 10 Pro
Mate 10 Pro will be available in a version with 6 GB of RAM and 64 GB or 128 GB of internal storage. The device is equipped with a dual main camera consisting of a 20 MP color and 12 MP monochrome sensor, with f/1.6 optical systems from Leica, optical stabilization images, phase and laser autofocus, HDR support and video recording in 2160p@30fps and 1080p@30/60fps formats. Front-camera has a resolution of 8 MP.
The Mate 10 Pro smartphone will immediately be presented under control latest version OS Android 8.0 (Oreo) with proprietary graphical interface Huawei EMUI 6.0. The device supports Wi-Fi networks standards 802.11 a/b/g/n/ac, Bluetooth 5.0 with A2DP, EDR and LE profiles, A-GPS navigation, GLONASS, BDS and GALILEO, NFC technology. There is also an IR port and a connector USB standard 2.0 Type-C.
Built-in non-removable lithium polymer battery The smartphone has a capacity of 4000 mAh.
Smart pen for Huawei Mate 10 Pro
Despite the ability to instantly digitize notes made on plain paper, the smart pen, which, according to preliminary data, will be included with the Mate 10 Pro, will not work as a stylus or pen for input. touch screen Huawei Mate 10 Pro, or will be equipped with additional input technology for these purposes.
Start of sales and price
No more or less clear information about the start of sales and price flagship smartphone There is no Huawei Mate 10 yet, everything will become known on Monday, September 16.
Announcement of the presentation of Huawei Mate 10 series smartphones
Preliminarily, network analysts estimate the cost of Huawei Mate 10 in China at $835, while the “regular” Huawei Mate 10 will cost about $650.
