Methods of organizing memory. Associative access memory Associative memory

A random access memory device, as a rule, contains many identical storage elements forming a storage array (SM). The array is divided into individual cells; each of them is designed to store binary code, the number of bits in which is determined by the width of the memory sample (in particular, it can be one, half or several machine words). The method of organizing memory depends on the methods of placing and searching for information in the storage array. Based on this feature, they distinguish between address, associative and stack (magazine) memories.

Address memory. In memory with an address organization, the placement and search of information in the memory is based on the use of the storage address of a word (number, command, etc.). The address is the number of the ZM cell in which this word is located.

When writing (or reading) a word into a memory, the command initiating this operation must indicate the address (cell number) at which the recording (reading) is performed.

A typical address memory structure contains a storage array of N-bit cells and its hardware frame, which includes an address register RgA having k (k» log N) digits, information register RGI, address sample block BAV, sense amplifier block BUS, block of bit amplifiers-formators of recording signals BUZ and memory management unit BUP.

By address code in RgA BAV generates signals in the corresponding memory cell that allow reading or writing a word in the cell.

The memory access cycle is initiated by an entry into BUP from outside the signal Appeal. The general part of the circulation cycle includes admission to RgA from the address bus SHA address and reception BUP and decoding of the control signal Operation, indicating the type of operation requested (read or write).

Further when reading BAV decrypts the address, sends read signals to the 3M cell specified by the address, while the code of the word written in the cell is read by the BUS read amplifiers and transmitted to RGI. The read operation is completed by issuing a word from RGI to the output information bus SHIVYH.

When recording, in addition to performing the above general part of the access cycle, the word being written is received from the input information bus SHIVh And RGI. Then to the selected BAV cell is written a word from RGI.

Control block BUP generates the necessary sequences of control signals that initiate the operation of individual memory nodes.

Associative memory. In this type of memory, the search for the necessary information is carried out not by address, but by its content (by associative characteristics). In this case, the search by an associative characteristic (or sequentially by individual bits of this characteristic) occurs in parallel in time for all cells of the storage array. In many cases, associative search can significantly simplify and speed up data processing. This is achieved due to the fact that in memory of this type, the operation of reading information is combined with the execution of a number of logical operations.

A typical structure of associative memory is shown in Fig. 4.3. The storage array contains N (n+1)-bit cells. To indicate the cell's occupancy, the nth service digit is used (0 - the cell is free, 1 - a word is written in the cell).

In associative storage devices, information is searched according to an associative feature recorded in each memory cell.

In this type of memory, the search for the necessary information is carried out not by address, but by the content of the information itself (i.e., by associative characteristics). In this case, the search for an associative feature occurs in parallel in time for all memory cells. Associative search can significantly simplify and speed up data processing. This is achieved due to the fact that in such memory the operation of reading information is combined with the execution of a number of logical operations. For example, you can perform operations such as:

1) search for the maximum or minimum number in the memory;

2) search for words within certain boundaries;

3) search for words closest to the associative feature, both on the larger and smaller sides, etc.

The simplest associative memory usually performs a single operation to select words whose feature matches the associative feature.

The storage array (SM) contains N cells, each cell has n+1 bits. To indicate cell occupancy, the nth service digit is used. If there is 0 in the nth bit, then the cell is free, if 1, then it is occupied.

Based on the input SD, an n-bit attribute is sent to the associative feature register RGP, and the search mask code is sent to the mask register RGM. In this case, the nth bit of the RGM register is set to 0. The associative search is performed only by those bits of the attribute that correspond to “1” in the mask register, that is, by the so-called unmasked RGM bits. Thus, by specifying the mask code M, you can arbitrarily select those bits of the attribute by which the search is carried out.

For words from the ZM in which all the digits coincided with the unmasked bits of the RGP, the combined circuit KS 1 sets “1” to the corresponding bits of the RGC match register. Thus, if the digit of the j-th word coincides with the unmasked bits of the attribute, then “1” will be written in the j-th bit of the RGC register, otherwise “0”. The entry “1” in the j-th digit of the RGC means that the j-th word corresponds to the attribute, i.e. is the word that is actually sought in ZM.

A word is written to the mask register that allows a query for all or only some bits of the associative attribute; using a mask allows you to shorten or expand the search area.

The search for information is carried out in parallel across all cells by comparing the request with the associative feature of each cell.

The search result is generated by a special combinational circuit that generates signals notifying about the absence of words that satisfy the search conditions, about the presence of only one word, about the presence of several words that have such an associative feature.

After generating and processing the warning signals, the control circuit reads the necessary information.

When recording information, a free cell is first found. To do this, an associative search operation is performed using a feature that has “0” in all bits, and in the mask register “0” is written in all bits except the lowest nth bit.

Thus, those 3M cells are determined that have “0” written in the nth digit, which means the cell is unoccupied. A word from the RGI information register is written to the free cell with the lowest number.

When using additional combinational circuits in associative memory, you can perform various logical operations, determining the maximum or minimum number, the number of words that have the same associative feature, etc. Figure 1 shows the structure of associative memory. The memory cells of an associative storage device must be elements of static memory; in associative memory, all cells are accessed simultaneously and must not be interrupted by regeneration cycles. Associative memory is the fastest, but very expensive, since it requires the introduction of an additional comparison circuit that allows searching for each memory cell. Therefore, such memory is usually not used in its pure form, and high-speed cache-type memory devices are usually implemented as partially associative.

In microprocessors, associative memory (memory with content selection) is used as part of cache memory to store the address portion of instructions and operands of the executable program. In this case, there is no need to contact RAM for the next command or the required operand; it is enough to place the required address in the associative attribute register and, if the required information is in the memory cache, it will be immediately issued. Access to RAM will be necessary only if the required information is not in the cache. Due to this use of the cache, the number of accesses to RAM is reduced, and this saves time, since accessing the cache requires approximately 10 times less time than accessing RAM.

Stacked memory organization

If writing and reading are done through the same register, then such a device is called stack memory, operating on the principle of “first in, last out” (FILO-First Input, Last Output).

Stack memory, like associative memory, is addressless; it is a collection of cells that form a one-dimensional array, in which neighboring cells are connected to each other by word transmission bit chains. Words are always written to the top zero cell. In this case, all previously recorded words are shifted down one cell. Reading is done in the reverse order of writing.

Stack memory has become widespread. To implement it in RAM, part of the memory is allocated for the stack using operating system programs. In practice, stack memory is often organized using regular address memory.

Let's consider the organization of stack memory as a memory formed from interconnected memory cells in which information is shifted down when a new word is written to the stack (Fig. 2). Information is exchanged only through the upper memory cell. When reading words from the stack, the word may be removed from stack memory or shifted around the ring, depending on the organization of the stack. Reading mode - last in, first out - is called LIFO (Last In First Out).

Fig. 2. Organization of stack memory.

Hardware implementation of such memory is not always advisable, and stack memory is often organized in the main memory of the computer in software, which allows you to change the stack size depending on need. When organizing a stack in main memory, a special address register is allocated - the “stack pointer”. The stack pointer contains the address of the last word written to the stack. When a word is written to the stack, the address of the top of the stack is automatically decreased, and when read, it is automatically increased. Stack memory is typically used to save the state of the current program when processing an interrupt. After the interrupting program is executed, the state of all registers that existed at the time the program was interrupted is restored in the reverse order of the write sequence. You can also save program data on the stack; this is convenient because when accessing the stack, you do not need to specify the addresses of memory cells in the program; information is also retrieved from the stack without specifying an address.

Ways to organize memory

Parameter name	Meaning
Article topic:	Ways to organize memory
Rubric (thematic category)	Computers

Functionally, memories of any type always consist of a storage array that stores information, and auxiliary, very complex blocks that serve for searching in the array, writing and reading (and, if required, for regeneration).

A storage array (SM) consists of many identical storage elements (SE). All electronic devices are organized into cells, each of which is designed to store a unit of information in the form of a binary code, the number of bits of which is determined by the sample width. The method of organizing memory depends on the methods of placing and searching for information in the memory. Based on this feature, they distinguish between address, associative and stack memory.

ADDRESS MEMORY

In memory with an address organization, the placement and search of information in the memory are based on the use of the storage address of a unit of information, which in the future for brevity we will call in a word. The address is the number of the ZM cell in which this word is located. When writing (reading) a word to a memory, the command initiating this operation must indicate the address (number) of the cell to which the write (read) is to be made.

In Fig. Figure 5.2 shows the general structure of address memory.

The memory access cycle is initialized by the “Access” signal arriving at the TCU. The general part of the access cycle includes receiving the access address from the address bus (ABA) and receiving the control signal “Operation” in the BUP, indicating the type of requested operation (reading or writing).

Reading. The BAS decrypts the address and sends a signal that selects the 3M cell specified by the address. In the general case, the BAS can also send signals to a selected memory cell that configure the electronic cells to write or read. After this, the word written into the cell is read by the BUS amplifiers and transmitted to the RgI. Next, in memory with destructive reading, information is regenerated by writing a word from the RgI through the BUZ into the same cell of the ZM. The reading operation is completed by issuing a word from RgI to the output information bus SHI out.

Record. In addition to the above general part of the access cycle, the written word is received from the input bus SHI in in RgI. The recording itself generally consists of two operations – clearing the cell and the recording itself. To do this, the BAS first selects and clears the cell specified by the address in RgA. Cleaning the CM cell (returning it to its original state) can be done in different ways. In particular, in memory with destructive reading, clearing can be done by a word read signal in the cell when the BUS is blocked (so that information does not enter the RgI). Next, a new word is written into the selected cell.

The need for the operation of clearing a cell before writing, as well as the operation of regenerating information when reading, is determined by the type of electronic devices used, control methods, and features of the electronic structure of the LSI memory; therefore, these operations may be absent in semiconductor memories.

The PCB generates the necessary sequences of control signals that initiate the operation of individual memory nodes. It should be borne in mind that the PCB must be a very complex device (a kind of control controller with its own cache memory), giving the memory LSI as a whole special consumer properties, such as multi-portability, pipelined information output, etc.

ASSOCIATIVE MEMORY

In this type of memory, information is searched not by address, but by its content. In this case, the content of information is usually understood not as the semantic load of a word stored in a memory cell, but as the content of the EE of the memory cell, ᴛ.ᴇ. bitwise composition of the written binary word. In this case, the associative request (sign) is also a binary code with a certain bit composition. Search by associative feature occurs in parallel in time for all 3M cells and is an operation of comparing the contents of the bits of the attribute register with the contents of the corresponding bits of memory cells. To organize such a search, all electronic devices are equipped with single-bit processors; therefore, in some cases, memory of this type is considered as a multiprocessor system.

Large-capacity fully associative memory is a very expensive device; therefore, to reduce its cost, the number of one-bit processors is reduced to one per memory cell. In this case, the comparison of the associative request with the contents of memory cells occurs sequentially for individual digits, parallel in time for all memory cells.

With very large amounts of memory on certain classes of problems, associative search significantly speeds up data processing and reduces the likelihood of computer failure. At the same time, associative memories with blocks of corresponding combinational circuits make it possible to perform quite complex logical operations in memory: searching for the maximum or minimum number in an array, searching for words enclosed within certain boundaries, sorting an array, etc.

It should be noted that associative search can also be implemented in a computer with regular address memory, sequentially calling words recorded in memory cells into the processor and comparing them with some associative feature (template). However, with large amounts of memory, this will take a lot of time. When using associative memory, it is possible, without reading words from the OP into the processor, to determine in one call the number of words that answer a particular associative request. This makes it possible to very quickly implement a query like: how many residents of the region have not submitted an income statement, etc., in large databases.

In some specialized computers, the OP or part of it is constructed in such a way that it makes it possible to implement both associative and address information search.

A simplified block diagram of associative memory, in which all electronic memory devices are equipped with single-bit processors, is shown in Fig. 5.3.

Let's first consider the operation called association control. This operation is common to the read and write operation and also has its own meaning.

An n-bit associative request, ᴛ.ᴇ, is received via the input information bus to RGAP. bits from 0 to n-1 are filled. At the same time, the search mask code is received in PrM, and the nth bit of PrM is set to 0. The associative search is performed only for the set of PrgAP bits, which correspond to 1 in PrgM (unmasked PrgAP bits). It is important to note that for words in which the digits in the digits coincide with the unmasked digits of RgAP, the CS sets 1 in the corresponding digits of RgSV and 0 in the remaining digits.

The combinational scheme for generating the result of associative reversal FS forms at least three signals from the word formed in RgSV:

A 0 – absence of words in the ZM that satisfy the associative criterion;

A 1 – the presence of one such word;

A 2 – presence of more than one word.

Other operations on the contents of RgSV are also possible, for example, counting the number of units, ᴛ.ᴇ. counting words in memory that satisfy an associative query, etc.

The formation of the contents of RgSV and a 0 , a 1 , a 2 according to the contents of RgAP, RgM, ZM is usually called the association control operation.

Reading. First, association control is carried out based on the characteristic in RgAP.

A 0 = 1 – reading is canceled due to lack of required information;

A 1 = 1 – the found word is read in RgI, after which it is output on the SHI output;

A 2 = 1 – a word is read that has, for example, the lowest number among the cells marked 1 in RgSV, and then is output to the SHI output.

Record. First, a free cell is found (we assume that the occupancy bit of the free cell contains 0). To do this, association control is performed at PrgAP = 111...10 and PrgM = 000...01, ᴛ.ᴇ. The nth digit of PrgAP is set to 0, and the nth digit of PrgM is set to 1. In this case, the free cell is marked 1 in PrgV. For recording, select a free cell, for example, with the lowest number. The word received from SHI input to RgI is recorded in it.

It should be noted that this diagram does not show the blocks BUP, BUS, BUS, which are found in real devices. At the same time, to build associative memory, storage elements are required that can be read without destruction.

STACK MEMORY (STORE)

Stack memory, like associative memory, is addressless. Stack memory must be organized both in hardware and on a regular addressable memory array.

In the case of hardware implementation, stack memory cells form a one-dimensional array in which neighboring cells are connected to each other by word transmission bit circuits (Fig. 5.4). In this case, two types of devices are possible (a, b), the principles of operation of which are different. Let us first consider the structure in Fig. 5.4, a.

A new word received from SHI input is written to the upper (zero) cell, while all previously written words (including the word in cell 0) are shifted down to adjacent cells, the numbers of which are one higher. Reading is possible only from the top (zero) memory cell. The main mode is reading with deletion. At the same time, all other words in memory are shifted upward, into adjacent cells with lower numbers. In such memory the rule is implemented: last one in, first one out. Stacks of this type are usually called LIFO (Last In – First Out) stacks.

In some cases, stack memory devices also provide the operation of simply reading a word from cell 0 without deleting it and shifting the remaining words. When using a stack to store the initialization parameters of controllers of any computer devices, it is usually possible to read the contents of any stack cell without deleting it, ᴛ.ᴇ. reading the contents of not only cell 0.

The first word pushed onto the stack is said to be located on bottom of the stack. The last word sent (in time) onto the stack is said to be in top of the stack. Τᴀᴋᴎᴍ ᴏϬᴩᴀᴈᴏᴍ, cell N-1 is the bottom of the stack, and cell 0 is the top.

Typically, the hardware stack is equipped with a stack counter SchSt, which shows the total number of words stored in memory (SchSt = 0 - the stack is empty). When the stack is full, it disables further writes.

The stack principle of memory organization can be implemented not only in devices specially designed for this. Stack-based data organization is also possible on regular addressable memory with random access (software stack). To organize a LIFO stack in this case, another memory cell (register) is needed, which always stores the address of the top of the stack and which is usually called stack pointer. Typically, one of the processor's internal registers is used as a stack pointer. In addition, appropriate software is required. The principles of stack data organization on conventional address memory are illustrated by the diagram in Fig. 5.5.

Unlike the hardware stack, data placed on the software stack does not move when a new number is written or read. Each new word is written to the memory cell next in order to the one whose address is contained in the stack pointer. After writing a new word, the contents of the stack pointer are incremented by one (see Figure 6.5). However, it is not the data that moves on the software stack, but the top of the stack. When a word is read from the stack, the reverse process occurs. The word is read from the cell whose address is in the stack pointer, after which the contents of the stack pointer are decremented by one.

If words newly loaded onto the stack are placed in memory cells with sequentially increasing addresses, the stack is called direct. If the addresses are sequentially decreasing, then – upside down. In most cases, an inverted stack is used, which is due to the peculiarities of the hardware implementation of counters inside the processor.

Why is this form of memory organization convenient? Looking ahead, we can note that any command executed in the processor, in the general case, must contain an operation code (OPC), the addresses of the first and second operands, and the address for storing the result. To save memory and reduce the time it takes for the processor to execute a machine instruction, it is desirable to reduce the instruction length. The limit to this reduction is the length of the addressless command, ᴛ.ᴇ. just COP. It is precisely such instructions that are possible with a stack memory organization, since if the operands are correctly located on the stack, it is enough to sequentially retrieve them and perform the appropriate operations on them.

In addition to the LIFO type stack memory discussed above, computers use stack memories of another type that implement the rule: first in, first out. Stacks of this type are usually called FIFO (First In – First Out) stacks. This stack memory is widely used to organize various kinds of queues (commands, data, requests, etc.). The generalized structure of a FIFO type hardware stack is shown in Fig. 5.4, b.

As in the previous case, stack memory cells form a one-dimensional array in which neighboring cells are connected to each other by bit word transfer circuits. A new word received from SHI input is written to the top (zero) cell, after which it immediately moves down and is written to the last unfilled cell. If the stack was empty before writing, the word immediately goes into cell number N-1, ᴛ.ᴇ. to the bottom of the stack. Reading is only possible from the bottom cell numbered N-1 (bottom of the stack). The main mode is reading with deletion. In this case, all subsequent (recorded) words are shifted down to adjacent cells whose numbers are one higher. When the stack is full, the counter (SchSt) prohibits further writes to the stack.

However, unlike the LIFO stack, in the FIFO stack it is not the bottom that moves, but the top. Words written to the FIFO stack gradually move from the top to the bottom, from where they are read as they are extremely important, and the rate of writing and reading is determined by external control signals and are not related to each other.

The software implementation of the FIFO stack is not discussed in this section, since it is used quite rarely in practice.

Methods of organizing memory - concept and types. Classification and features of the category "Methods of organizing memory" 2017, 2018.

Our memory is inherently associative. This is expressed in the fact that a single memory can recall another, another - a third, etc., forcing or allowing thoughts to move from one to another along a chain of mental associations. Associative memory is a connection between the circumstances and ideas of an individual. Associations are a kind of invisible hooks that extract from the depths of experience, circumstances, and ideas accumulated in memory, experienced moments (what happened) and connect them with what needs to be remembered.

Associative theory of memory

There are several areas of psychology related to memory. The main ones among them are associative, behavioristic, cognitive, and activity. They all agree that memory is the process of remembering, storing and reproducing information and forgetting it, and that memory is the basis in the process of personality formation.

At the same time, based on its principles, each of the theories of memory explains in its own way the essence and patterns of this process.

One such theory is the associative theory of memory. It comes from the idea that association is nothing more than a connection that takes place between mental phenomena. When memorizing, such connections are established between parts of the memorized or reproduced material. The fact is that in the process of remembering a person is always looking for some connections established between the material that is available and the one that needs to be reproduced.

Some patterns have been identified on the basis of which associations are formed:

— By contiguity. It occurs if the perceived image is associated with past experienced ideas or with those that were simultaneously experienced and associated with this image, that is, on the basis of association with previous material. For example, remembering our school, we will most likely remember our class teacher or a school friend and the emotions associated with them, and remembering a work colleague, we may remember that next Saturday is a working Saturday, and we need to remember to set an alarm for the weekend morning.

- By similarity. Have you noticed that, for example, some people resemble someone? Maybe it has happened to you, looking at a stranger, to find a certain “type” in him or to discover that his features (face, demeanor, posture, etc.) will be remembered by you because he looks like...? For example, clumsy, shaggy, with a waddling gait - like a bear; small, homely, timid and defenseless in appearance - like a sparrow; bright, important, with straightened shoulders and slow, important movements - like a peacock.

- By contrast. It is very easy for us to associate “white - black”, “good - evil”, “fat - skinny”. They are also produced by our associative memory and used to consolidate the image. In this case, the perceived images extract opposing ideas from consciousness. So, when faced with an irritated neighbor, you remember how calm her sister seems.

The disadvantage of the associative theory of memory is that it does not explain such an important characteristic as the selectivity of memory (after all, associative material is not always remembered well). In addition, it does not take into account that memory processes depend on the organization of the memorized material.

The development of associative memory, as well as associative thinking, is very important: associations help us remember and remember, and generate ideas. Associative memory allows us to remember words and complex texts that are not related to each other; thanks to it, we more easily extract the necessary information from memory and the more extensive the network of associative connections, the better it is remembered and the easier it is to recall when necessary. Our judgments about a particular issue, our views, tastes, and value systems are based on associative memory. Our thinking, perception of the world and decision-making are also connected with it.

Associative memory is trained by linking known, already learned information with new material. To develop associative memory, you can use, for example, the following exercise:

1. Prepare 2 sheets of paper and a pen. On 1 sheet of paper, write all the natural numbers from 1 to 100 in a vertical column.

2. Select any 10-15 of them with which you have strong associations, and write them down in random order on sheet 2. For example, 8 is a snowman, 17 is the number of your favorite minibus, 18 is the age of majority in the country in which you live (if so), etc. After you finish your work, wait 5-7 minutes, take 1 piece of paper with numbers and write down all the events that you remember opposite the corresponding number.

3. Next time, do the same with other numbers not used before. Don’t force things, don’t push yourself too hard at first, try to choose as successfully as possible an association that will reliably take its place on the list.

4. When the entire list of numbers is completed, test yourself by indicating all associations associated with numbers from 1 to 100.

In addition to training your memory, you have created additional associations that will help you remember codes, phone numbers, etc. if necessary. Just try to use your personal associations without being afraid to draw on images. For example, 40 can be remembered by imagining 4 as a square, a “TV”, and 0 as a circle inscribed in it, a “bun”. The result is a funny association of “bun on TV.” Come up with your own associations that are suitable for you.

Speaking about the development of memory, it should be noted that it is inextricably linked with attention, because without focusing attention on an object, we will not move it even to short-term memory. Good memory function requires high neuronal activity and well-coordinated functioning of the cognitive functions of the brain. You can read more about the development of memory and attention.

Memory and attention, perception and thinking are brain functions that are subject to training and development. Thanks to regular exercises, you can significantly improve your abilities, and it is better to give preference to regular complex exercises with gradually increasing load. For example, for this purpose it is convenient to use classes on.

We wish you success in self-development!

Photo: Laurelville - Camp & Retreat Center

A storage device, as a rule, contains many identical storage elements forming a storage array (SM). The array is divided into individual cells; each of them is designed to store binary code, the number of bits in which is determined by the width of the memory sample (in particular, it can be one, half or several machine words). The method of organizing memory depends on the methods of placing and searching for information in the storage array. Based on this feature, they distinguish between address, associative and stack (magazine) memories.

Address memory. In memory with an address organization, the placement and search of information in the memory is based on the use of the storage address of a word (number, command, etc.), the address is the number of the memory cell in which this word is located.

When writing (or reading) a word into a memory, the command initiating this operation must indicate the address (cell number) at which the recording (reading) is performed.

A typical address memory structure shown in Fig. 4.2, contains a storage array of N n-bit cells and its hardware frame, including the address register RgA, having k(k> log 2 N) digits, information register RgI, address sample block BAV, sense amplifier block BUS, block of bit amplifiers-formators of recording signals BUZ and memory management unit BUP.

Fig. 4.2. Address memory structure.

By address code in RgA BAV generates signals in the corresponding memory cell that allow reading or writing a word in the cell.

The memory access cycle is initiated by an entry into BUP from outside the signal Appeal. The general part of the circulation cycle includes admission to RgA s address bus SHA address and reception BUP and decoding of the control signal Operation, indicating the type of operation requested (read or write).

Further when reading BAV decrypts the address, sends read signals to the cell specified by the address ZM, in this case, the code of the word written in the cell is read by reading amplifiers BUS and transmitted to RgI. Then in memory with a destructive read (when read, all storage elements of the cell are set to the zero state). information is regenerated in a cell by writing to it from RGI a few words. The read operation is completed by issuing a word from RGI to the output information bus SHIVIkh.

When recording, in addition to performing the above general part of the access cycle, the word being written is received from the input information bus SHIVh V RgI. The recording itself consists of two operations: clearing the cell (resetting to 0) and the recording itself. For this BAV first selects and clears the cell specified by the address in RgA. Clearing is performed by the word read signals in the cell, but this blocks the sense amplifiers and from BUS V RGI no information is received. Then to the selected BAV cell is written a word from RgI.

Control block BUP generates the necessary sequences of control signals that initiate the operation of individual memory nodes. The control signal transmission circuits are shown with thin lines in Fig. 4.2.

A typical structure of associative memory is shown in Fig. 4.3. The storage array contains N(P + 1) - bit cells. To indicate the cell's occupancy, the nth service digit is used (0 - the cell is free, 1 - a word is written in the cell).

By input information bus SHIVh to the associative attribute register RgAP goes to 0-and-1 digits P- bit associative query, and into the mask register RgM - search mask code, with the nth digit RgM is set to 0. Associative search is performed only for a set of bits RgAP, which "correspond to 1 in RgM(unmasked bits RgAP). For words in which the digits in the digits coincide with the unmasked digits RgAP, combinational circuit KS sets 1 to the corresponding bits of the match register RgSV and 0 in the remaining digits. So the value j-ro rank in RgSV is determined by the expression

RgSV(j) =

Where RgAP[i], RgM[i] and ZM - values of the i-th digit, respectively RgAP, RgM and jth cell ZM.

Combination scheme for generating the result of an associative appeal FS forms from a word formed in RgSV, signals  0,  1,  2, corresponding to cases of absence of words in ZM, satisfying the associative criterion, the presence of one or more than one such word. For this FS implements the following Boolean functions:

 0 =

 1 = РгСв

 2 =  0  1

Content generation RgSV and signals  0,  1,  2 by content RgAP, RgM And ZM is called an association control operation. This operation is an integral part of the read and write operations, although it has its own meaning.

When reading, the association is first checked according to the associative feature in RgAP. Then at  0 = 1 reading is canceled due to the absence of the required information, when  1 = 1 it is read into RGI found word, with  2 = 1 in RGI a word is read from the cell that has the lowest number among the cells marked 1 in RgSv. From RGI the read word is given out on SHIVIkh.

Rice. 4.3. Structure of associative memory

When recording, a free cell is first found. To do this, an association check operation is performed when PrgAP= 111. ..10 and RgM== 00... 01. In this case, free cells are marked 1 in RgSv. The free cell with the lowest number is selected for recording. It records the word received from SHIVh V RgI.

Rice. 4.4. Stack memory

Using the association control operation, you can, without reading words from memory, determine by content RgSV, how many words are in memory that satisfy an associative criterion, for example, implement queries like how many students in a group have an excellent grade in a given discipline. When using appropriate combinational circuits, quite complex logical operations can be performed in associative memory, such as searching for a larger (smaller) number, searching for words contained within certain boundaries, searching for a maximum (minimum) number, etc.

Note that associative memory requires storage elements that can be read without destroying the information recorded in them. This is due to the fact that during associative search, reading is performed throughout the entire SM for all unmasked bits and there is no place to store information that is temporarily destroyed by reading.

stack memory, just like associative, it is addressless. IN stack memory(Fig. 4.4) the cells form a one-dimensional array in which neighboring cells are connected to each other by word transmission bit circuits. A new word is written to the top cell (cell 0), while all previously written words (including the word that was in cell 0) are shifted down to adjacent cells with numbers larger by 1. Reading is possible only from the top (zero) memory cell, and if reading with deletion is performed, all other words in memory are shifted upward to adjacent cells with higher numbers. In this memory, the order of reading words follows the rule: last to arrive - first served. A number of devices of this type also provide for the operation of simply reading a word from the zero cell (without deleting it and shifting the word in memory). Sometimes stack memory is provided with a stack counter SchSt, showing the number of words stored in memory. Signal Schst = 0 corresponds to empty, stack, Schst = N - 1 - full stack.

Stack memory is often organized using address memory. Stack memory is widely used when processing nested data structures.

The following paragraphs of the chapter describe various types of addressable storage devices. Associative memory is used in equipment for dynamic distribution of OP, as well as for constructing cache memory.