Using the post card pci tester from the nm9221 master kit for PC diagnostics. PCI bus protocol

Each transaction (exchange on the bus) involves two devices - the initiator of the exchange, also known as the master device, and the target device, also known as the slave. The PCI bus treats all transactions as packets: each transaction begins with an address phase, which can be followed by one or more data phases. The composition and purpose of the bus interface signals are given in Table. 1.

Table 1. Composition and purpose of PCI bus interface signals.

At any given time, the bus can only be controlled by one master device, which has received the right to do so from the arbiter. Each master device has a pair of signals - REQ# to request bus control and GNT# to confirm that bus control has been granted. The device can start a transaction (set the FRAME# signal) only when the received GNT# signal is active. Removing the GNT* signal prevents the device from starting the next transaction, and under certain conditions (see below) causes it to terminate the current transaction. Arbitration of requests to use the bus is handled by a special node included in the chipset motherboard. The priority scheme (fixed, round-robin, combined) is determined by the arbiter programming.

Common multiplexed AD lines are used for address and data. Four multiplexed C/BE lines provide command encoding in the address phase and byte resolution in the data phase. At the beginning of a transaction, the master device activates the FRAME# signal, transmits the target address via the AD bus, and information about the type of transaction (command) via the C/BE# lines. The addressed control center responds with the DEVSEL# signal. The master device indicates its readiness to exchange data with the IRDY# signal; this readiness can be set before receiving DEVSEL#. When the control center is ready to exchange data, it will set the TRDY# signal. Data is transmitted on the AD bus only when the IRDY# and TRDY# signals are simultaneously present. With the help of these signals, the master device and the control center coordinate their speeds by introducing wait cycles. In Fig. Figure 1 shows a timing diagram of the exchange in which both the master device and the control center enter wait cycles. If they both entered the ready signals at the end of the address phase and did not remove them until the end of the exchange, then 32 bits of data would be transmitted in each clock cycle after the address phase, which would provide maximum exchange performance.

The number of data phases in the packet is not explicitly indicated, but before the last data phase, the master device, when the IRDY# signal is inserted, removes the FRAME# signal. In single transactions, the FRAME# signal is active for only one clock cycle. If the device does not support batch transactions in slave mode, then it must request that the batch transaction be terminated during the first data phase (by entering the STOP# signal at the same time as TRDY#). In response, the master will complete the given transaction and continue to exchange the subsequent transaction with the new address value. After the last data phase, the host device removes the IRDY# signal and the bus enters the idle state (PCI Idle) - both the FRAME# and IRDY# signals are in a passive state. The initiator can start the next transaction without a rest period by entering FRAME# simultaneously with withdrawing IRDY#. Such fast adjacent transactions (Fast Back-to-Back) can be addressed either to one or to different central centers. The first type is supported by everyone PCI devices, acting as a control center. The initiator is allowed (if he knows how) to use fast adjacent transactions with different devices(bit 9 of the command register), only if all bus agents allow fast calls.

Rice. 1. Communication cycle on the PCI bus

The handshake protocol ensures the reliability of the exchange - the master device always receives information about the processing of the transaction by the central control center. A means of increasing reliability (validity) is the use of parity control: lines AD and C/BE# in both the address phase and the data phase are protected by the parity bit PAR (the number of unit bits of these lines, including PAR, must be even). The actual PAR value appears on the bus with a delay of one clock cycle relative to the AD and C/BE# lines. When a CPU error is detected, the PERR# signal is generated (with a clock shift after the validity of the parity bit). When calculating parity when transmitting data, all bytes are taken into account, including invalid ones (marked by a high level of the C/BEx# signal). The bit state, even in invalid data bytes, must remain stable during the data phase.

Each transaction on the bus must be completed as planned or aborted, and the bus must go into a rest state (the FRAME# and IRDY# signals are passive). The completion of a transaction is carried out either at the initiative of the master or at the initiative of the PU. The master can complete the transaction in one of the following ways:

Normal termination (Camletiori) is performed when the data exchange is complete.

A time-out occurs when, during a transaction, the master's control of the bus is taken away (by removing the GNT# signal) and the time specified in its Latency Timer expires. This can happen if the addressed CU is unexpectedly slow or the transaction is scheduled to be too long. Short transactions (with one or two data phases), even if the GNT# signal is removed and the timer is triggered, are completed normally.

A transaction is rejected (Master-Abort) when the master does not receive a response from the CPU (DEVSEL#) within a specified time.

The transaction can be terminated at the initiative of the Control Center; To do this, it can enter a STOP# signal. There are three types of termination possible:

Retry - the STOP# signal is entered when the TRDY# signal is passive before the first data phase. This situation occurs when the control center, due to internal busyness, does not have time to issue the first data on time (16 clock cycles). A retry is an indication to the master to start the same transaction again.

Disconnect - The STOP# signal is entered during or after the first data phase. If the STOP# signal is entered while the TRDY# signal of the next data phase is active, then this data is transmitted and the transaction is completed. If the STOP# signal is entered with a passive TRDY# signal, then the transaction is completed without transmitting the data of the next phase. Disconnection occurs when the control center is unable to timely issue or receive the next portion of packet data.

Target-Abort - the STOP# signal is entered simultaneously with the DEVSEL# signal being removed (in previous cases, when the STOP# signal appeared, the DEVSEL# signal was active). After this, the data is no longer transmitted. A refusal is introduced when the control center detects a fatal error or other conditions under which it will no longer be able to service a given request.

Bus commands, memory and I/O addressing

Each bus command specifies the address of the data transmitted in the first data phase of the packet. The address for each subsequent data phase of the packet is incremented by 4 (next double word), but in memory access instructions the order may be different (see below). The AD bus bytes carrying valid information are selected by the C/BE# signals in the data phases. Within a packet, these signals can change state from phase to phase in an arbitrary manner. Allowed bytes may be scattered; There may be data phases in which no bytes are allowed. Unlike the ISA bus, there is no dynamic bit change on PCI - all devices must be connected to the bus in a 32-bit manner. If the PCI device uses functional circuits of a different capacity (for example, you need to connect an 8255 chip that has an 8-bit data bus and four registers), then you have to adopt circuit conversion methods that map all registers to the 32-bit AD bus.

Addressing memory, ports and configuration registers are different.

♦ In memory access cycles, the address aligned on a double word boundary is transferred along the AD lines; AD lines specify the order of addresses in the packet:

00 - linear increment; the address of the subsequent phase differs from the previous one by the number of bus bytes (4 for a 32-bit and 8 for a 64-bit bus).

10 - Cacheline Wrap mode, address wrapping taking into account the length of the cache line. In a transaction, the address for the next phase is increased until it reaches the cache line boundary, after which it moves to the beginning of this line and increases to the address preceding the start one. If the transaction longer than the line cache, then it will continue in next line from the same offset as it started. So, with a line length of 16 bytes and a 32-bit bus, a transaction that starts at address xxxxxxOSh will have subsequent data phases related to addresses xxxxxxOCh, xxxxxxOOh, xxxxxx04h; and further to xxxxxxlSh, xxxxxxlCh, xxxxxxlOh, xxxxxx!4h. The cache line length is specified in the device configuration space (see section 6.2.12). If the device does not have a Cache Line Size register, then it must abort the transaction after the first data phase;

01 and 11 - reserved, can be used as an indication to disconnect (Disconnect) after the first data phase.

In cycles of accessing I/O ports, all AD lines are used to address any byte. In this case, the AD address bits indicate the double word address to which the transmitted data belongs, and the low-order bits of the AD address must correspond to bytes that can be enabled by C/BE# signals. When AD=00, C/BE# is allowed - xxxO or 1111, with AO «01-C/BE# = xx01 or 1111, with AO=10-C/BE# = x011 or 1111, with AD=11 - C/BE# = 0111 ( only byte 3) or 1111 is transmitted (no bytes are allowed). These cycles can also be batched, although in practice this feature is rarely used.

In configuration write/read cycles, the device (expansion card) is selected by an individual IDSEL signal; the function is addressed by AD bits, and the configuration registers (doublewords only) are addressed by AD bits, with AD=00.

Teams PCI buses are determined by the values ​​of the C/BE# bits in the address phase.

Interrupt acknowledge command designed to read the interrupt vector. According to the protocol, it looks like a read command, implicitly addressed to the system interrupt controller. Here, in the address phase, no useful information is transmitted via the AD bus, but its initiator (main bridge) must ensure signal stability and correct parity. In a PC, an 8-bit vector is transmitted in byte 0 when the interrupt controller is ready (via the TRDY# signal). Interrupt confirmation is performed in one cycle (the first idle cycle, which x86 processors do as a tribute to antiquity compatibility, is suppressed by the bridge).

Special cycle differs from all others in that it is broadcast. However, no agent responds to it, and the main bridge or other device that introduces this cycle always ends it using the Master Abort method (it requires 6 bus cycles). A special cycle is designed to generate broadcast messages- they can be read by any “interested” bus agents. The message type is decoded by the contents of the AD lines; the AD lines can contain the data carried in the message. The address phase in this cycle is for conventional devices is missing, but bridges use its information to control message propagation. Messages with codes OOOOh, 000lh, and 0002h are required to indicate a shutdown, a processor halt, or specific x8b processor functions related to cache and trace. Codes 0003-FFFFh are reserved. A special cycle can be generated by the same hardware and software mechanism as configuration cycles (see section 6.2.11), but with a specific address value.

Read and Write I/O Commands serve to access the port space. The AD lines contain the byte address, and the ADO and AD1 bits are also subject to decoding (despite the fact that BEx# signals are present). PCI ports can be 16-bit or 32-bit. All 32 address bits are available for addressing ports on the PCI bus, but x86 processors can only use the lower 16 bits.

Memory Access Commands, in addition to normal read and write, include reading cache lines, multiple reads (multiple lines), invalid writes.

Configuration read and write commands are addressed to the device configuration space (see clause 6.2.12). Addresses are made only in double words. The structure contains the device identifier and output for, state and command, information about occupied resources and restrictions on bus use. To generate these commands, a special hardware and software mechanism is required (see section 6.2.11).

Reading memory lines is applied, when more than two 32-bit transfers are scheduled in a transaction (usually a read to the end of the cache line).

Multiple memory reads are used for cross-boundary transactions cache lines.

Record with invalidation applies to entire cache lines and allows optimization of writeback cycles of dirty cache lines.

♦ Two-address cycle allows you to access devices with 64-bit addressing via a 32-bit bus. In this case, the lower 32 bits of the address are transmitted in a cycle of this type, followed by a regular cycle that determines the type of exchange and carries the most significant 32 bits of the address. The PCI bus allows 64-bit addressing of I/O ports (this is useless for x86, but PCI exists on other platforms).

S/BE Command Type

0000 Interrupt Acknowledge - interrupt confirmation

0001 Special Cycle - special cycle

0010 I/O Read - reading the I/O port

0011 I/O Write - writing to the I/O port

0100 Reserved

0101 Reserved

0110 Memory Read - reading memory

0111 Memory Write - writing to memory

1000 Reserved

1001 Reserved

1010 Configuration Read - configuration reading

1011 Configuration Write - configuration write

1100 Multiple Memory Read - multiple memory reading

1101 Dual Address Cycle (DAC)

1110 Memory-Read Line - reading a memory line

1111 Memory Write and Invalidate - record with invalidation.

Organization of direct memory access. Purpose, implementation and control tasks of a direct memory access controller.

Direct memory access (DMA) is one of the ways to exchange data with the PU. In this mode, data exchange between the control unit and the memory of the microprocessor system occurs without the participation of the processor. Exchange in DMA mode is controlled not by a program executed by the processor, but by a special device external to the processor, called a DMA controller (KPDC). DMA is used for fast input/output of data blocks and offloading the processor from managing I/O operations. Exchange of data blocks using software-controlled exchange is relatively slow, since several processor instructions are spent on exchanging each byte. The DDP frees the processor from managing I/O operations, thereby allowing the processor to execute a program in parallel in time with data exchange between the PU and memory, and to carry out this exchange at a speed limited only by the bandwidth of the memory or PU. Thus, the DMA, by relieving the processor from servicing I/O operations, helps to increase the overall performance of the microprocessor system.

To implement the DMA mode, it is necessary to ensure direct communication between the DMA controller and the memory of the microprocessor system, i.e. a special information channel through which exchange is carried out in the DDP mode - the DDP channel. For this purpose, you can use a specially dedicated highway connecting the DMA controller to the memory. However, such a solution cannot be considered optimal, since it will lead to a significant complication of the microprocessor system as a whole, especially when connecting several control units. In order to reduce the number of lines in the microprocessor system buses, the DMA controller is connected to the memory via system buses. This raises the problem of sharing system buses between the processor and the DMA controller. There are two main ways to solve it:

implementation of exchange in DMA mode with cycle capture;

implementation of exchange in DMA mode with processor blocking.

There are two flavors of loop-snatching DMA. The simplest way to organize DAP is that the processor cycles in which it does not exchange data with memory are used for exchange. During such cycles, the DMA controller can communicate with memory without interfering with the processor. However, there is a need to allocate such cycles so that there is no temporary overlap of DMA exchange with exchange operations initiated by the processor. Some processors generate a special control signal to indicate cycles in which the processor is not using memory. If the processor does not generate such a signal, then to allocate free cycles it is necessary to use a special circuit in the DMA controller, which leads to the complication of the latter. The use of this method of organizing DAP does not reduce the performance of the system, but exchange in the DAP mode is possible only at random times in single words.

The most common is DMA with cycle capture and forced disconnection of the processor from the system bus. To implement this DMA mode, the system bus is supplemented with two control signals - “Request for direct memory access” HOLD and “Provide direct memory access” HLDA.

The HOLD control signal is generated by the DMA controller. The processor, having received this signal, suspends the execution of the current command without waiting for its completion, disconnects from the system buses and issues the HLDA control signal to the DMA controller. From this moment on, all system buses are controlled by the DMA controller. The DMA controller, using the system bus buses, exchanges one word of data with the memory and then, after removing the HOLD signal, returns control of the system bus to the processor. As soon as the DMA controller is ready to exchange the next word of data, it again seizes the processor cycle, and so on. In the intervals between cycle captures by the DMA controller, the processor continues to execute program commands. Thus, program execution slows down, but to a much lesser extent than when exchanging in interrupt mode.

Transferring a block of data using DDP involves performing a certain sequence of actions (Fig. 32):

initial installation ( preliminary preparation) DPM controller;

launching the DDP controller;

occupying a processor cycle multiple times;

completion of the exchange.

Rice. 32 – Algorithm for transmitting a data block using a DDP controller

The program is used only for the initial installation and start of exchange through the DDP channel. The processor can then execute the main program, which is not associated with the exchange. During the execution of this program, each time a request is received for the DMA, the DMA controller will occupy a processor cycle and perform a transfer. After the end of the exchange, an interrupt is used to transfer control to the exchange completion program in the DMA mode. The main program can then continue.

Let's consider the organization of the DMA controller, which provides data input into the memory of the microprocessor system in the DMA mode (Fig. 33).

Rice. 33 – Organization of the DPM controller

The initial preparation for exchange in the DMA mode consists of allocating to the PU the memory area used in the exchange and indicating its size, i.e. the number of words of information written to memory or read from memory. Therefore, the DMA controller must include an address register and a word counter. Before starting an exchange with the PU in the DMA mode, the processor must execute a loading program that ensures that the starting address of the memory allocated by the PU and its size in words of a given bit depth are written to the specified registers of the DMA controller.

Thus, before starting to input the next block of data from the PU, the processor loads the following information into the registers of the DMA controller: into the word counter - the number of received words, and into the address register - the starting address of the memory area for the input data. Thus, the controller is prepared to perform the operation of entering data from the PU into memory in the DMA mode.

The DPM controller is started by an output command, which sets the start trigger to 1. The start trigger connects the PU to the DMA controller. After the start command of the DMA controller there must be an interrupt enable command. In the future, the data block is entered through the DDP channel without the participation of program commands.

When the PU prepares a data word, it is sent to the controller data register. In this case, each word is accompanied by a control signal from the “Data Input” control unit, which ensures that the data word is written to the controller’s data register. Using the same signal (when the start trigger is set to 1), a request trigger is set to 1, the signal from the output of which is sent to the input of the processor “Direct memory access requirement” HOLD. After the processor generates the response signal “Providing direct memory access” HLDA, the next machine cycle is occupied by the exchange. In this case, one transfer of a data word is carried out to a memory cell at the address located in the controller’s address register. Based on the HLDA signal, the controller exposes the contents of its address and data registers to the address and data buses of the system bus, respectively. By generating the control signal MEMWR, the DMA controller ensures that a word of data is written from its data register to memory. The HLDA Direct Memory Access Grant signal is also used in the controller to perform three operations:

reset request trigger;

increasing the contents of the address register by 1;

Decrease the contents of the word counter by 1.

For each HLDA signal, 1 is subtracted from the contents of the word counter, and when it becomes equal to 0, the end of data block transfer trigger is set to 1, the output signal of which is used as an interrupt request and is sent to the corresponding processor input. The processor interrupts program execution and transfers control to the interrupt routine to complete the exchange.

The exchange is completed by disconnecting the PU from the DPM controller with an output command, which resets the start trigger to 0. In addition, the end of data block transmission trigger is reset to 0 in the same way. When the interrupt is processed, control returns to the main program.

If there is no need to continue executing a program in parallel with transmission in DMA mode, it is used as a ready signal, which is available to the processor through the status register of the DMA controller. In this case, the interrupt is not used (the output of the transfer end trigger is not connected to the interrupt request input of the processor or the interrupt in the processor is disabled). During the exchange through the DMA channel, the processor is in a cycle of waiting for the end of the transfer, polling the corresponding readiness bit of the status register of the DMA controller upon an input command. As soon as the processor detects readiness, it proceeds to the exchange completion procedure (step 4 of the sequence discussed above), after which program execution continues.

Completion of the exchange by disconnecting the PU from the DPM controller - resetting the start trigger to 0 - can be carried out not by an output command in the interrupt processing subroutine, but automatically when the contents of the word counter become equal to 0 (as well as setting the transfer end trigger to 1). In this case, there is no need for a start trigger in the DPM controller, and the connection/disconnection of the PU to the controller is carried out depending on the state of the word counter. When loading the number of received words into the counter, the “0=” signal is set to 1 and connects the control signal from the “Data Input” control panel to the S input of the request trigger. After all words have been transmitted, the contents of the counter become equal to 0, the “0=” signal is reset to 0 and prohibits the flow of the control signal from the “Data Input” PU to the S input of the request trigger, thereby disconnecting the PU from the DPM controller.

Above, only the process of preparing the DPM controller and directly transferring data in the DPM mode were discussed. In practice, any data exchange session with a PU in the DDP mode always also includes the stage of preparing the PU for exchange. At this stage, the processor, in a program-controlled exchange mode, polls the state of the PU, checking its readiness for exchange, and sends commands to the PU to ensure its preparation for data exchange via the DMA channel. Such preparation can be reduced, for example, to moving the heads to the required track in the NMD. Then the registers of the DMA controller are loaded, after which data exchange in the DMA mode begins either at the initiative of the DMA controller, as discussed above, or at the initiative of the PU.

It should be noted that the use of exchange in the DMA mode with cycle capture in a microprocessor system requires the programmer to have a very clear understanding of the processes occurring in the system during program execution and clear synchronization of the program execution process and input/output via the DMA channel.

Direct memory access with processor lock differs from the DMA mode with cycle capture in that control of the system bus is transferred to the DMA controller not for the duration of the transfer of one word, but for the duration of the exchange of a data block. This DMA mode is necessary in cases where the time between two “Direct Memory Access Request” HOLD signals is comparable to a processor cycle. In this case, the processor does not have time to execute at least one command between subsequent exchange operations in the DMA mode.

In a microprocessor system, you can use several control units operating in the DMA mode. The provision of system buses to such PUs for data exchange is carried out on a priority basis. In this case, PU priorities are implemented in the same way as when exchanging data in interrupt mode. As a rule, each PU uses its own pair of control signals “Request for direct memory access” HOLD and “Provide direct memory access” HLDA and a separate channel in the DMA controller.

Von Neumann (Princeton) and Harvard architecture. Organization of memory and I/O spaces. Basic methods for reducing energy consumption of microprocessor computers.

Under organization understand the composition of components (hardware or software), the relationships between them and their functional characteristics.

The computer has a multi-level hierarchical organization with its own components at each level:

1) Lower level− level of physical components − physical organization (represented in the form of a circuit diagram);

2) the level of functions implemented in a computer - logical (functional) organization (represented in the form of a functional diagram);

3) top level− hardware level (composition, functional connections and characteristics of hardware modules) − structural organization(presented in the form of a block diagram).

All components of a microprocessor system are represented to the processor as a set of memory cells or input/output ports, which form two main spaces: memory space and input/output space, respectively.

Von Neumann (Princeton) and Harvard architecture. Most modern microprocessor systems use a common memory bus to store programs and data. This organization was called the architecture of J. von Neumann, who proposed coding programs in a format corresponding to the data format. Computers with this architecture are called von Neumann or Princeton type machines. In them, areas for storing programs (Program Space - PS) and data (Data Space - DS) form a single space and can be located anywhere in the shared memory. In this case, there are no signs indicating the type of information in the memory cell. The contents of the cell are interpreted by the CPU, and it is the programmer's job to ensure that the data and the program are treated differently. Von Neumann architecture is typical for universal MPs.

Custom MTs and microcontrollers use a different design known as the Harvard Lab or Harvard architecture. In its classic version, programs and data are stored in two separate memories, which allows the fetching and execution of commands to be completely combined in time. Computers designed in accordance with the concept of dividing memory into two types are called Harvard-type machines. In such systems, program memory and data memory are separated and have their own address spaces and ways to access them. The program is always in one memory, and the data is in another. This separation makes it possible to increase performance and simplify the circuit implementation of a microprocessor system.

Further improvement of both types of architectures consisted of the allocation of a special small data space, which is a set of software-accessible registers (Register Space). Unlike memory and I/O ports, registers are always located inside the MP along with the ALU, which provides quick physical access to the information stored in them. At certain time intervals, the program works most intensively with only a small amount of data. The register area is intended for temporary storage of this data - a set of programmatically accessible registers.

The register area can be either completely isolated from the DS data space or partially overlap with it, which makes it possible to consider individual MP registers as ordinary data memory cells. Such an organization is appropriate if the MP supports fast access to all or at least some part of the data memory.

All modern MPs have register areas, regardless of what type they belong to: Princeton or Harvard. The internal logical organization of the register area is very diverse and depends on the type of MP. The functional structure of the register area will be discussed later. For now, we will note only one register in its composition, which is called the program counter PC (Program Counter). This register is mandatory for all MPs and is associated with addressing program memory. It serves as a pointer to the next element of the program sequence to be fetched and executed.

The I/O space represents a set of addressable buffer circuits and registers, called ports, through which communication with external and internal hardware of the microprocessor system is carried out.

A microprocessor system can use two options for organizing I/O space:

Isolated I/O. I/O ports are located in a special input/output space (IOS), isolated from other data spaces. In this case, the MP has special set input/output commands.

combined I/O or memory-mapped I/O. In this case, there is no isolated I/O space, and the DS data memory space is allocated to areas where the ports are located. Organizing access to ports in such a microprocessor system is no different from the process of accessing data in memory.

In Fig. Figure 4 shows four typical sets of areas for storing programs and data. The arrows show the process of isolating individual areas, leading to the emergence of a new typical set. All sets exist in reality, each has its own advantages and disadvantages, taking into account which allows you to create highly efficient systems for various purposes.

In contrast to the register area, the PS program memory space and DS data memory space, as well as the IOS I/O area, are organized more simply. The memory is a linearly ordered set of n-bit random access cells (one-dimensional array) - linear memory. All cells are numbered, so each cell in the set has a number called its address. All addresses occupy an integer range from 0 to 2 m -1 (m is the address width), which forms the memory address space. In most cases, the processor can address memory with one byte precision, i.e. The smallest addressable unit is a byte and memory has a byte organization.

Rice. 4 – Areas of the microprocessor for storing programs and data

The organization of memory space is shown in Fig. 5. In this case, the memory is depicted in such a way that cells with high addresses are located lower than those with low ones. The numbering of individual digits in a cell is done from right to left, starting from zero, with the digit with the zero number being the least significant.

Rice. 5 - Organization of memory space

Program objects (instructions and operands) can be longer than one byte, for example, two bytes is a 16-bit word or just a word, four bytes is a 32-bit word or double word, eight bytes is a 64-bit word or quad word. Such objects are located in adjacent cells of memory space, with the low byte usually located in the cell with the lower address. The address of an object is the smallest of the addresses of the cells occupied by it, i.e. in this case, the address of its low byte. This order is called Little-Endian Memory Format. It is used in microprocessors with x86 architecture. Other families of processors also use the reverse order - Big-Endian Memory Format, in which objects are located in adjacent memory cells, starting with the high byte, and low bytes are placed in subsequent cells (for example, in microcontrollers of the 68HC11 family from Motorola). In this case, the object's address is the address of its high byte. For mutual conversion of object formats, processors have special commands. A memory access operation involves reading or writing the entire object as a whole. For example, 16-bit words in memory are stored in two adjacent cells. The high byte of a word occupies a cell with a higher address, and the low byte occupies a cell with a lower address. In this case, the address of the low byte serves as the word address (see Fig. 5).

Often, memory organization imposes certain restrictions on the possible location of multibyte objects. For example, words in memory can only be at even addresses. Then, when accessing a word, the value of the low-order bit of its address, which points to a byte in the word, is not taken into account, i.e. such memory has a word limit.

For example, in the 8086 MP, any two contiguous bytes in memory can be treated as a 16-bit word. Thus, data words can be freely placed at any address, which saves memory due to its dense packaging. However, to save program execution time, it is advisable to place data words in memory at even addresses, since the MP transmits such words in one bus cycle. Words with odd addresses (not aligned) are also acceptable, but their transmission requires two bus cycles, which reduces MP performance. It is especially important to have aligned words for stack operations, since they involve only words. Therefore, the SP stack pointer must always be initialized to an even address. Instructions in the 8086 MP are always fetched by words at even addresses, with the exception of the first fetch after control transfer to an odd address, when one byte is fetched. The instruction stream is divided into bytes within the MP, so instruction alignment does not affect performance and is therefore not used.

In Intel processors starting from 486, at privilege level 3, control of the alignment of operands along the appropriate boundary can be enabled: a word at an even address, a double word at an address that is a multiple of four, and a quadruple word at an address that is a multiple of eight. At privilege levels 0, 1, 2, alignment control is not performed.

The considered organization of memory corresponds to the lower (physical) level of memory representation. The I/O space has the same organization. There is a higher (logical) level of memory organization at which the programmer works and which is associated with the architecture of the processor.

Backbone-modular principle of organizing a microprocessor system. Most modern microprocessor systems are built on a backbone-modular principle. In accordance with this principle, the memory and input/output subsystem are implemented in the form of separate functionally complete modules that are connected to a single intra-system backbone.

The memory subsystem consists of read only memory (ROM) modules, which are used to store programs and constants, and random access memory (RAM) modules, which are used to store variables and externally loaded programs.

In the simplest case, the IC subsystem consists of buffer circuits and registers addressed to the MP - input/output ports. They are designed to communicate with simple external devices such as LEDs, switches, etc. More complex I/O subsystem modules, designed to control external interface equipment and implement special I/O functions, are built on the basis of I/O ports and are called adapters or peripheral controllers.

The most complex of the input/output subsystem modules are input/output processors (coprocessors), which operate on their own programs stored in memory and are essentially separate microprocessor systems.

Depending on the method of connecting individual modules of the microprocessor system to the system bus, three typical structures of microprocessor systems are distinguished:

mainline;

main-cascade;

main-radial.

In the backbone structure, all modules of the memory and I/O subsystems are connected directly to the system backbone. This is the simplest structure. The disadvantages of the mainline structure are:

all modules must support an exchange protocol over the system bus and contain means of interface with it, which, depending on the microprocessor, can be quite complex;

low performance, because Slow peripheral devices can occupy the system backbone for a long time.

In backbone-cascade and backbone-radial structures, individual modules are connected using special bus controllers (adapters), the main purpose of which is to implement priority relationships when using the backbone.

In a backbone-cascade structure, individual modules are connected to the bus controller using an additional common channel, for example, a backbone or I/O bus, i.e. according to the main circuit. In a backbone-radial structure, each module is connected to the bus controller using an individual channel, i.e. according to a radial scheme.

Architecture with bus hierarchy. Currently, two methods of construction are approximately equally widespread computers: Directly coupled and bus-based.

In systems built using the first method, there are direct connections between interacting devices (processor, memory, input/output device). Features of connections (number of lines in buses, bandwidth, etc.) are determined by the type of information, the nature and intensity of the exchange. The advantage of architecture with direct connections can be considered the possibility of decoupling bottlenecks by improving the structure and characteristics of only certain connections, which can be the most economically beneficial solution. In von Neumann computers, such a bottleneck is the data transfer channel between the processor and memory, and it is quite difficult to decouple it. In addition, systems with direct connections are difficult to reconfigure.

In the common bus option, all computer devices are connected to the system bus, which serves as the only path for command, data, and control flows. The presence of a common bus significantly simplifies the implementation of a computer and makes it easy to change the composition and configuration of the machine. Thanks to these properties, bus architecture has become widespread in microcomputers. At the same time, the main drawback of the architecture is associated with the bus: at any time, only one device can transmit information via the bus. The main load on the bus comes from exchanges between the processor and memory associated with retrieving commands and data from memory and writing calculation results into memory. Only a portion of the bus bandwidth is available for I/O operations. Practice shows that even with a fast enough bus for 90% of applications, these residual resources are usually not enough, especially in the case of input or output of large amounts of data.

Therefore, while maintaining the von Neumann concept of sequential execution of program commands, the bus architecture in its pure form turns out to be insufficiently effective. A bus hierarchy architecture is more common, where in addition to the system bus there are several additional buses. They can provide direct communication between the most heavily trafficked devices, such as the processor and cache. Another option for using additional buses is to combine input/output devices of the same type with subsequent output from the additional bus to the system bus. This allows you to reduce the load on the common bus and use its bandwidth more efficiently. The most widespread are microprocessor systems with one bus, two or three types of buses.

In single-bus structures, there is one system bus that provides information exchange between the processor and memory, as well as between input/output devices, on the one hand, and the processor or memory, on the other. This approach is characterized by simplicity and low cost. However, a single-bus organization is not able to provide high communication speeds, and the bus becomes the bottleneck.

Although I/O device controllers can be connected directly to the system bus, greater effect is achieved by using one or more I/O buses. I/O devices are connected to I/O buses, which handle the bulk of the traffic not associated with output to the processor or memory. The connection is made using bus adapters, which provide buffering of data as it is sent between the system bus and I/O device controllers. This allows a microprocessor system to support multiple input/output devices and simultaneously decouple information exchange along the processor-memory path from information exchange with input/output devices. Such a scheme significantly reduces the load on the high-speed processor-memory bus and helps to increase the overall performance of the microprocessor system.

A high-speed expansion bus can be added to the bus system to connect high-speed peripheral devices. I/O buses are connected to the expansion bus, and from there through an adapter to the processor-memory bus. The circuit further reduces the load on the processor-memory bus. This arrangement of buses is called mezzanine architecture.

Features of the organization CISC architectures and RISC. Main advantages and disadvantages.

Any computer repairman knows that the POST Card PCI is used to diagnose problems when repairing and upgrading computers such as IBM PC (or compatible ones).

Several companies produce such cards in Russia and the CIS: Master Kit (Moscow), e-KIT Post Cards, ACE Lab (N. Novgorod), BVG Group (Moscow), EPOS: PCI TESTCARD (Ukraine), IC Book: IC80 (Ukraine ), Jelezo: Jpost Full (Ukraine), VL Comp: PC Analyzer (Belarus). There are also foreign solutions, but we cannot find them on the open market.

POST Card PCI is a computer expansion card that can be installed in any free PCI slot (33 MHz) and is designed to display POST codes generated by the computer BIOS in a user-friendly form.

Conventionally, all POST cards can be divided into serial and non-serial (kits for self-assembly).

Review of existing POST cards

Let's look at the disadvantages of POST cards from various manufacturers.

The founder of the production of PCI POST cards in Russia is considered to be the company ACE Lab, which has a large presence in the production of software and hardware systems for diagnostics and repair of computers.

Master Keith POST Card PCI NM9221 (DIY kit)/BM9221 (finished board). One drawback is that the seven-segment indicator faces downwards.

Advantages of this POST Card: assembled on an FPGA of the EPM3XXX series, supporting Hot-socketing (more reliable, since there is less chance of burning the POST Card) and operating at 3.3V (better compatibility with modern PCI2.3 and PCI3.0 specifications), support for new and old chipsets thanks to removable firmware.

e-Kit_02 Disadvantages of this POST Card: it is assembled on an FPGA of the outdated EPM7XXX series, which does not support Hot-socketing (less reliable, since there is a greater chance of burning the POST Card) and operates at 5.0V (there may be problems with modern PCI2.3 and PCI3.0).

ACE Lab PC-POST PCI-2. It is not convenient that the indicator looks down, but it is possible to select one of 4 possible ports from which information will be read.

ACE Lab PC POWER PCI-2— a fully functional software and hardware complex that allows you to perform a number of diagnostic tests launched from the ROM installed on the board, aimed at identifying system errors and hardware conflicts.

BVG Group Dual POST. Advantages: simple and cheap POST card. Made on the basis of FPGA Altera EPM3032ALC44-10. It carries five LEDs (power supply to PCI - -12V, +12V, +3.3V, +5V, and RESET signal) and two seven-segment indicators on both sides of the board. The indicator may show one digit - this means that the PCI slot into which this POST is inserted is not receiving clocking.

A characteristic disadvantage of this card due to its stripped-down nature is the removal of clocking from the PCI slot in which this card is installed after the POST stage, at which the generator is initialized (for Award BIOS- 26h), as a result of which the postcodes are no longer displayed. The methods of “fighting” this disease are as follows:

• If in BIOS Setup there is a Detect DIMM/PCI Clock item - setting it to Disable will prevent the generator from removing the frequency from unused slots, as a result of which Dual POST will work “as normal” ;), showing all the “relying” postcodes.
• If the board being tested has Sharing PCI Slots (usually two connectors farthest from the processor, which have one interrupt “for two”), then you can insert any “normal” PCI device (video, audio, network, etc.) into one of them .), and in the other - a postcard. During initialization, the generator, seeing a “full-fledged” PCI device on the Sharing PCI Slots, often (depending on the specific BIOS board) does not remove the clock from both, which Dual POST will successfully “take advantage of”.

BVG Group POST Pro. Instead of seven-segment displays, an LCD display with a ticker is used, but the cost of the card is about 300 USD, which is unreasonably high.

EPOS: PCI TESTCARD. Advanced “Master” series of useful bells and whistles by and large It only allows you to additionally select a diagnostic port in the range 0-3FFh, which is used to output POST codes, using switches on the board. Disadvantages of this POST Card: it is assembled on an FPGA of the outdated EPM7XXX series, which does not support Hot-socketing (less reliable, since there is a greater chance of burning the POST Card) and operates at 5.0V (there may be problems with modern PCI2.3 and PCI3.0). There is also information about the output of incorrect POST codes on some motherboards.

IC Book: IC80. Famous representative“adult” postcards, the distinctive feature of which is the presence of not only “bells and whistles” in the field of monitoring, but also unique (unparalleled) capabilities for debugging the system in a step-by-step mode. The board has several distinctive features:

• Selection of addresses used for diagnostic purposes: 80h/81h and 84h/85h, 378h, 1080h
• Diagnostic codes are displayed on two indicators
• Displaying information on an external indicator
• Voltage indication Stand-By 3.3V
• PCI parity support
• Support for server PCI bus options

Minor drawback: does not work quite correctly step by step mode on new boards.

Jelezo: Jpost Full. On some motherboards (mainly GIGABYTE) it freezes to a black screen after the first reboot.

VL Comp: PC Analyzer. A simple and cheap post-controller, the highlight of which is the combination of two types of postcards in one design - for ISA and for PCI.

POST Card PCI BM9222 with LCD Display

Today we will look at the PCI POST card of the new generation POST Card PCI BM9222 manufactured by the Moscow company Masker Kit.

Specifications

• Supply voltage: +5 V.
• Current consumption, no more than: 100 mA.
• PCI bus frequency: 33 MHz.
• Diagnostic port address: 0080h
• Indication of POST codes: on the LCD display in two lines of 16 characters each (the first line is the POST code in hexadecimal and separated by a dash - the BIOS type, the second line is a description of the error in the form of a creeping line).
• Indication of PCI bus signals: LEDs on the front side of the board - RST (PCI reset signal) and
• CLK (PCI clock signal).
• Voltage indicators PCI power supply buses: +5V, +12V, -12V, +3.3V.
• Compatible with motherboard chipsets: Intel, VIA, SIS.
• PCB size: 95.5 x 73.6 mm.

Design

Structurally, the POST Card PCI is made on a double-sided printed circuit board made of foil fiberglass with dimensions of 95.5 x 73.6 mm. In order to improve the electrical conductivity of the device contacts, the lamellas are coated with nickel.

Operating principle of POST Card PCI

Every time you turn on the power of your IBM PC-compatible computer and before the operating system boots, the computer's processor runs a BIOS procedure called POST (Power On Self Test). The same procedure is also performed when you press the RESET button or when you soft restart the computer. To avoid misunderstandings, it should be noted here that in some special cases In order to reduce computer boot time, the POST procedure can be slightly shortened, for example, in the “ Quick Boot"or when resuming Hibernate's sleep mode.

The main purpose of the POST procedure is to test the basic functions and subsystems of the computer (such as memory, processor, motherboard, video controller, keyboard, flexible and hard drives etc.) before loading the operating system. This to some extent protects the user from trying to work on a faulty system, which could lead, for example, to the destruction of user data on the HDD. Before starting each test, the POST procedure generates a so-called POST code, which is output to a specific address in the address space of the computer's input/output devices. If a fault is detected in the device under test, the POST procedure simply freezes, and the pre-printed POST code uniquely determines which test the freeze occurred on. Thus, the depth and accuracy of diagnostics using POST codes is completely determined by the depth and accuracy of the tests of the corresponding POST BIOS procedure of the computer.

It should be noted that the POST code tables are different for different BIOS manufacturers and, due to the emergence of new tested devices and chipsets, are somewhat different even for different versions of the same BIOS manufacturer. Tables of POST codes can be found on the corresponding websites of BIOS manufacturers: for AMI this is http://www.ami.com, for AWARD - http://www.award.com, sometimes tables of POST codes are given in the manuals for motherboards.

To display POST codes in a user-friendly form, devices called POST Card are used. The proposed POST Card for the PCI bus is a computer expansion card that is inserted (with the power off!) into any free PCI slot (33 MHz) and has a text indicator for displaying POST codes and text information about current code. Among the operating features of this POST Card, I would like to note that after turning on the computer’s power and before the first active RESET PCI signal appears, the greeting message “BM9222 MASTERKIT POSTCARD” is displayed on the POST Card indicator.

In addition, the POST Card has LEDs that reflect the status of the CLK and RST signals of the PCI bus.

Troubleshooting using POST Card PCI

The sequence of actions when repairing a computer using a POST Card is as follows:

1. Turn off the power to the faulty computer.
2. Install the POST Card into any free PCI slot on the motherboard.
3. Turn on the computer's power.
4. If necessary, adjust the contrast (when installing an LCD screen, for PLED - no adjustment required) of the image by pressing the buttons (the button farthest from the motherboard increases the contrast, the closest one decreases) or change the type of displayed BIOS - by pressing and holding one of the buttons and clicking on the second (after releasing the buttons, the BIOS type will change, displayed in the first line of the indicator after the error code). All of the above settings are saved when the power is turned off and loaded the next time power is applied to the POST Card.
5. We read the information on the POST Card indicator - this is the POST code on which the computer boots “hangs”, and its description in the second line.
6. We comprehend the probable reasons.
7. With the power off, we rearrange the cables, memory modules and other components in order to eliminate the malfunction.
8. Repeat steps 3-7, ensuring stable completion of the POST procedure and the start of loading the operating system.
9. Using software utilities We carry out final testing of hardware components, and in case of floating errors, we carry out a long run of the corresponding software tests.

When repairing a computer without using POST Card points 3-6 of this sequence are simply omitted and from the outside, computer repair looks like just a frantic rearrangement of memory, processor, expansion cards, power supply, and, to top it all, the motherboard.

If large companies have a large supply of serviceable components, then for small companies and individuals, computer repair by installing known-good components turns into a complex problem.

How is a computer repaired using a POST-Card carried out in practice?

First of all, when the power is turned on, before the POST procedure can begin, the system must be reset with the RST (RESET) signal, which is indicated on the POST Card by changing the greeting message to other POST Card messages. If the change does not occur within 2-4 seconds (the welcome display time is approximately 0.7 seconds) or one of the “NO CODES” or “RESET” messages appears for more than 1 second, then in this case it is recommended to immediately turn off the computer, remove all cards and cables, as well as memory modules from the motherboard. IN system unit You must leave the motherboard with the processor installed and the POST Card connected to the power supply. If the next time you turn on the computer, the system resets normally and the first POST codes, then obviously the problem lies in the temporarily removed computer components; it is also possible in incorrectly connected loops. By sequentially inserting the memory, video adapter, and then other cards, and observing the POST codes on the indicator, a faulty module is detected.

Let us now return to the case when the initial system reset does not even go through (the POST Card indicator does not change the greeting message to other messages). In this case, either the computer's power supply is faulty, or the motherboard itself (the RESET signal generation circuits are faulty) or the processor does not start. The exact cause can be determined by connecting a known-good power supply to the motherboard.

Let us now consider the case when the reset signal passes, but no POST codes are displayed on the indicator (the “NO CODES” message is held); in this case, as described earlier, a system consisting only of a motherboard, processor, POST Card and power supply is tested. If the motherboard is completely new, then the reason may be incorrectly installed motherboard jumpers. If all jumpers and the processor are installed correctly, but the motherboard still does not start, you should replace the processor with a known good one. If this does not help, then we can conclude that the motherboard or its components are faulty (for example, the cause of the malfunction may be damaged information in the FLASH BIOS).

The main advantage of the POST Card is that it does not require a monitor to operate. At the same time, testing a computer using a POST Card is possible in the early stages of the POST procedure, when sound diagnostics are not yet available. Another important feature is the display of POST codes on all types of BIOSes that output codes at address 0x0080), but not described in the ROM.

PLED indicator

This testing device is equipped with an indicator with a PLED type display element. The advantages of this type of display are that it has high contrast and a wide viewing angle - this is very important because often a POST card has to be installed in a computer case when other cards (network, sound, etc.) are installed in adjacent slots.

Multilingual support

The POST card allows you to display codes for various types of BIOS in various languages ​​(English and Russian by default). Changing the BIOS type is carried out by simultaneously pressing both buttons at once. This post the card decrypts 3 types of BIOSes in 2 languages ​​(6 types in total). The Russified BIOS contains the string “RU” in its name.

The lines themselves describing the codes are located on the 24C256 - 32kB SEEPROM chip. This microcircuit is installed in the socket, and experienced users can extract it and reprogram it with another (newer or different language) version if it appears on the website www.masterkit.ru. Updates occur regularly, tracking trends in the development of computer technology.

If this code is not decrypted in your version, then you should use the Internet to quickly search for a decryption of the test type, and also write a letter to the MasterKit company indicating this case, and in the next version this code will be included.

To reprogram, you can use the NM9215 (programmer) kit together with an adapter for this type NM9216/4 chips.

Testing a PC system unit with a Post Card PCI tester in practice

The sequence of testing computer components is as follows:

1. CPU testing.
2. Check checksum ROM BIOS.
3. Check and initialize DMA, IRQ and 8254 timer controllers.
After this stage, sound diagnostics become available.
4. Checking memory regeneration operations.
5. Testing the first 64 KB of memory.
6. Loading interrupt vectors.
7. Initialization of the video controller.
After this stage, diagnostic messages are displayed on the screen.
8. Testing the full amount of RAM.
9. Keyboard testing.
10. Testing CMOS memory.
11. Initialization of COM and LPT ports.
12. Initialization and test of the FDD controller.
13. Initialization and test of the HDD controller.
14. Search for additional ROM BIOS modules and initialize them.
15. Calling the operating system loader (INT 19h, Bootstrap), if the operating system cannot be loaded, try to launch ROM BASIC (INT 18h); if unsuccessful, system shutdown (HALT).

Taking tests

When passing each of the POST tests, a POST code is generated, which is written to a special diagnostic register. The information contained in the diagnostic register becomes available for observation when the POST Card diagnostic board is installed in a free computer slot and is displayed on a seven-segment display in the form of two hexadecimal digits. The diagnostic register address depends on the type of computer, in older versions it is: ISA, EISA-80h, ISA-Compaq-84h, ISA-PS/2-90h, MCA-PS/2-680h, 80h, some EISA-300h.

First of all, you need to determine the manufacturer Motherboard BIOS fees. This can be done either by a sticker on the BIOS chip, or by the inscriptions that are displayed on the screen by a similar working motherboard. In Russia and the CIS, the most common BIOS are AMI and AWARD. Once you have gained some experience, you can confidently name the BIOS manufacturer based on the first POST codes.

POST code tables are different for different BIOS manufacturers and, due to the emergence of new tested devices and chipsets, are different even for different versions of the same BIOS manufacturer.

Historically, the values ​​of POST codes in the corresponding tables of BIOS manufacturers are given as hexadecimal numbers in the range 00h-FFh (0-255 in decimal system notation), therefore, for ease of use of such tables, it is necessary to ensure the display of POST codes in hexadecimal form.

Fault codes

Award Software International, Inc.

AwardBIOS V4.51PG Elite

The dynamically developing company Award Software in 1995 proposed a new solution at that time in the field of low-level software, AwardBIOS “Elite,” better known as V4.50PG. The control point maintenance mode has not changed either in the widespread version V4.51 or in the rare version V4.60. The suffixes P and G denote support for the PnP mechanism and support for energy saving functions (Green Function), respectively.

Executing startup POST procedures from ROM

C0 External Cache prohibition. Internal Cache prohibition. Shadow RAM ban. Programming DMA controller, interrupt controller, timer, RTC block

C1 Determining the type of memory, total volume and placement by lines

C3 Checking the first 256K DRAM for the Temporary Area organization. Unpacking BIOS in Temporary Area

C5 Running POST code is moved to Shadow

C6 Determining the presence, size and type of External Cache

C8 Checking the integrity of BIOS programs and tables

CF Determining the processor type

Performing a POST in Shadow RAM

03 Disable NMI, PIE (Periodic Interrupt Enable), AIE (Alarm Interrupt Enable), UIE (Update Interrupt Enable). Prohibition of generation of programmable frequency SQWV

04 Checking the generation of requests for DRAM regeneration

05 Checking and initializing the keyboard controller

06 Test the memory area starting at address F000h, where the BIOS is located

07 Checking CMOS and battery operation

BE Programming the configuration registers of the South and North Bridges

09 Initializing the L2 Cache and Advanced Cache Control Registers on the Cyrix Processor

0A Generation of interrupt vector table. Configuring Power Management Resources and Setting the SMI Vector

0B Checking the CMOS checksum. Scanning PCI bus devices. Processor microcode update

0C Initializing the Keyboard Controller

0D Finding and initializing the video adapter. Setting up IOAPIC. Clock measurements, FSB setting

0E MPC initialization. Video memory test. Displaying the Award Logo

0F Testing the first DMA 8237 controller. Keyboard detection and internal test. BIOS checksum verification

10 Checking the second DMA 8237 controller

11 Checking DMA controller page registers

14 System Timer Channel 2 Test

15 Test of the request masking register of the 1st interrupt controller

16 Interrupt controller 2 request masking register test

19 Checking the Passivity of an NMI Interrupt Request

30 Determining the volume of Base Memory and Extended Memory. APIC setup. Software control Write Allocation mode

Preparing tables, arrays and structures for starting the operating system

31 The main on-screen RAM test. Initialization

32 The Plug and Play BIOS Extension splash screen appears. Setting up Super I/O resources. Programmable Onboard Audio Device

39 Programming the clock generator via the I2C bus

3C Setting the software flag to allow entry into Setup

3D Initializing PS/2 mouse

3E External Cache Controller Initialization and Cache Permissions

B.F. Setting up chipset configuration registers

41 Initializing the floppy disk subsystem

42 Disable IRQ12 if PS/2 mouse is missing. The hard drive controller is being soft reset. Scanning other IDE devices

43 Initializing serial and parallel ports

45 Initializing the FPU coprocessor

4E Display of error messages

4F Password Request

50 Restoring a previously stored CMOS state in RAM

51 Resolution of 32 bit access to HDD. Configuring ISA/PnP Resources

52 Initialization additional BIOS. Setting the values ​​of PIIX configuration registers. Formation of NMI and SMI

53 Setting the DOS Time counter according to Real Time Clock

60 Installing BOOT Sector antivirus protection

61 Final steps to initialize the chipset

62 Reading keyboard ID. Setting its parameters

63 Correction of ESCD, DMI blocks. Clearing RAM

FF Transferring control to the bootloader. BIOS executes INT 19h command

Let's consider the procedure for testing the system unit of a personal computer. Let's install the BM9222 tester into a free PCI slot on the motherboard. Let's turn on the power. BIOS is a computer boot program stored in the motherboard ROM that sequentially polls all devices included in the system unit (processor, memory modules, hard drive, video card, controllers, optical drive, external peripherals: keyboard, mouse, etc.).

If all peripheral devices of the system unit are working properly, then after loading is complete, the following inscription FFh will light up on the tester screen.

“Let’s introduce a fault” into the system unit. Turn off the power and remove the memory module from the system unit.

After power is applied and the computer boots, the RAM error code 4Eh appears on the tester screen.

The tester accurately determined that the memory in the system unit is “faulty.” After turning off the power and returning the memory module to its place, the tester showed the health of the personal computer.

Similarly, you can determine the error codes of other peripheral devices and quickly resolve the problem by replacing the faulty unit with a working one.

conclusions

Each transaction (exchange on the bus) involves two devices - the initiator of the exchange, also known as leading(master) device, and target (target) device (DC), also known as slave(slave). The PCI bus treats all transactions as packets: each transaction begins with an address phase, which can be followed by one or more data phases. The composition and purpose of the bus interface signals are given in Table. 6.11.

Table 6.11. PCI bus signals

At any given time, the bus can only be controlled by one master device, which has received the right to do so from the arbiter. Each master device has a pair of signals - REQ# to request bus control and GNT# to confirm that bus control has been granted. The device can start a transaction (set the FRAME# signal) only when the received GNT# signal is active. Removing the GNT# signal prevents the device from starting the next transaction, and under certain conditions (see below) causes it to terminate the current transaction. Arbitration of requests to use the bus is handled by a special node included in the motherboard chipset. The priority scheme (fixed, round-robin, combined) is determined by the arbiter programming.

Common multiplexed AD lines are used for address and data. Four multiplexed C/BE lines provide instruction encoding in the address phase and byte resolution in the data phase. At the beginning of a transaction, the master device activates the FRAME# signal, transmits the target address via the AD bus, and information about the type of transaction (command) via the C/BE# lines. The addressed control center responds with the DEVSEL# signal. The master device indicates its readiness to exchange data with the IRDY# signal; this readiness can be set before receiving DEVSEL#. When the control center is ready to exchange data, it will set the TRDY# signal. Data is transmitted on the AD bus only when the IRDY# and TRDY# signals are present simultaneously. With the help of these signals, the master device and the control center coordinate their speeds by introducing wait cycles. In Fig. Figure 6.7 shows a timing diagram of the exchange in which both the master device and the control center enter wait cycles. If they both entered the ready signals at the end of the address phase and did not remove them until the end of the exchange, then 32 bits of data would be transmitted in each clock cycle after the address phase, which would provide maximum exchange performance.

Rice. 6.7. Communication cycle on the PCI bus

The number of data phases in the packet is not explicitly indicated, but before the last data phase, the master device, when the IRDY# signal is inserted, removes the FRAME# signal. In single transactions, the FRAME# signal is active for only one clock cycle. If the device does not support batch transactions in slave mode, then it must request that the batch transaction be terminated during the first data phase (by entering the STOP# signal at the same time as TRDY#). In response, the master will complete the given transaction and continue to exchange the subsequent transaction with the new address value. After the last data phase, the master removes the IRDY# signal and the bus goes into a rest state ( PCI Idle) - both signals FRAME# and IRDY# are in a passive state. The initiator can start the next transaction without a rest period by entering FRAME# at the same time as withdrawing IRDY# . Such fast adjacent transactions (Fast Back-to-Back) can be addressed either to one or to different central centers. The first type is supported by all PCI devices acting as a central control unit. Support of the second type (it is optional) is indicated by bit 7 of the status register (see section 6.2.12). The initiator is allowed (if he can) to use fast contiguous transactions with different devices (bit 9 of the command register) only if all bus agents allow fast access.

The bus allows you to reduce the power (current) consumed by devices, at the cost of reduced performance, by using step-by-step line switching AD and PAR (address/data stepping). There are two possible options here.

Smooth step (continuous stepping) - the beginning of signal formation by weakly accurate shapers several clock cycles before the introduction of a valid information qualifier signal (FRAME# in the address phase, IRDY# or TRDY# in the data phase). During these few clock cycles, the signals will “crawl” to the required value at a lower current.

Discrete stepping - normal shapers are not triggered all at once, but in groups (for example, byte-by-byte), in each clock cycle one group at a time. At the same time, current surges are reduced, since fewer drivers are switched at the same time.

The device itself may not use these capabilities (see bit 7 of the command register), but must “understand” such cycles. By delaying the FRAME# signal, a device risks losing access to the bus if the arbiter receives a request from a higher-priority device.

The handshake protocol ensures the reliability of the exchange - the master device always receives information about the processing of the transaction by the central control center. A means of increasing reliability (validity) is the use of parity control: lines AD and C/BE# in both the address phase and the data phase are protected by the parity bit PAR (the number of single bits of these lines, including PAR, must be even). The actual PAR value appears on the bus with a delay of one clock cycle relative to the AD and C/BE# lines. When a CPU error is detected, the PERR# signal is generated (with a clock shift after the validity of the parity bit). When calculating parity when transferring data, all bytes are taken into account, including invalid ones (marked high level signal C/BEx#). The bit state, even in invalid data bytes, must remain stable during the data phase.

Each transaction on the bus must be completed as planned or aborted, and the bus must go into a rest state (the FRAME# and IRDY# signals are passive). The completion of a transaction is carried out either at the initiative of the master or at the initiative of the PU.

The master can complete the transaction in one of the following ways.

Normal completion ( Completion) is executed upon completion of data exchange.

Completion due to timeout ( Time-out) occurs when, during a transaction, the master's right to control the bus is taken away (by removing the GNT# signal) and the time specified in its Latency Timer expires. This can happen if the addressed CU is unexpectedly slow or the transaction is scheduled to be too long. Short transactions (with one or two data phases), even if the GNT# signal is removed and the timer is triggered, complete normally.

The transaction is rejected ( Master-Abort) when the master does not receive a response from the control center (DEVSEL#) within a specified time.

The transaction may be terminated by initiative of the Central Control Center; To do this, it can enter the STOP# signal. There are three types of termination possible.

Repeat ( Retry) - the STOP# signal is entered with a passive TRDY# signal before the first data phase. This situation occurs when the control center, due to internal busyness, does not have time to issue the first data on time (16 clock cycles). A retry is an indication to the master to start the same transaction again.

Disable ( Disconnect) - the STOP# signal is entered during or after the first data phase. If the STOP# signal is entered while the TRDY# signal of the next data phase is active, then this data is transmitted and the transaction is completed. If the STOP# signal is entered with a passive TRDY# signal, then the transaction is completed without transmitting the data of the next phase. Disconnection occurs when the control center is unable to timely issue or receive the next portion of packet data.