Post code d1 what to do. POST BIOS error codes diagnostics using POST card

POST-codesAward BIOS Medallion V 6.0

POST code (hex) Check completed

Performing POST startup procedures from Flash BIOS

CF Early detection of processor type. Recording results in CMOS. CMOS read/write functional test.

If processor type detection or CMOS writing fails, a fatal operation error is set and POST execution is stopped.

C0 Chipset pre-initialization.

Prohibition of shadow RAM areas, disabling L2 cache. Clear L1 cache.

Programming the following basic chipset registers.

Interrupt controllers: receive on IRQ edge, Master Controller - IRQ 00h=INT 8...IRQ 7=INT 0Fh, Slave Controller - IRQ 8= INT 70h...IRQ 15=INT 77h.

DDP controllers.

Interval timer: Counter 0 - frequency division mode by 65,536 (18.2 Hz) to generate IRQ 0 system clock requests. Counter 1 - generation of pulses for DRAM regeneration (128 cycles are performed in 2 ms or the interval between regeneration of two lines is about 15 μs). Counter 2 - used to sound the system speaker.

The RTC is initialized if there is a battery power failure. If there was no Vcc (bat) failure, then only the registers responsible for the interaction between the RTC and the processor are initialized, but not the clock

	Checking the type, size, high address and ECC of RAM. Checking the first 256 KB of RAM.
	Organization in this area of a transit buffer, into which from Flash BIOS
	Boot Block is copied to verify checksums
	Checking the BIOS checksum and the presence of the BBSS tag. If the checks are incorrect,
	a decision is made about partial damage to the Flash BIOS IC. If checks
	are correct, the system BIOS unpacking program is copied to the buffer
	Unpacking the system BIOS into RAM, copying the optional system into RAM
	BIOS. Preparing for BIOS Shadowing
	Copy the executable POST code to the shadow RAM area E000h-F000h.
	Transfer control to the Boot Block module.
	Start POST from shadow RAM.

Checking the integrity of the BIOS structure. If the checksums for checking the BIOS service fields match, the RAM check continues, otherwise control is transferred to the BIOS recovery programs

Performing POST on Shadow RAM )

1 At physical address 1000:0000h, the BIOS module is unpacked - the XGROUP program, which allows you to set all the resources of the motherboard, including the system timer, interrupt controllers and DMAs, a mathematical coprocessor and a default video controller

3 Performing early initialization of the Super I/O chip, the first stage was performed in algorithm steps CFh and C0h

5 Setting the initial attributes of the video system.

Checking the CMOS status flag, its contents are reset

7 Reset the input and output buffers of the keyboard controller (8042 or 8742 compatible). The controller is part of the Super I/O system chip

fees. Self-test, initialization of the keyboard controller. Keyboard interface connection allowed

	Prohibits the connection of the PS/2 computer mouse interface.
	The type of keyboard interface is determined (PS/2 or AT/DIN). Programmable
	keyboard controller. Keyboard allowed
	The PS/2 mouse interface is not yet allowed.
	For some systems - determining the ports to which the PS/2 keyboard is connected
	and mouse, which may cause port reassignment
	Checking the shadow segment F000h with read and write cycles. This area
	will be used for DMI and ESCD. If the check is incorrect, then
	a sound signal is generated and error code EFh is output to port 0080h
	If the written and read data from the F000h segment do not match,
	an error is detected and the POST execution is stopped

10 Determining the type of installed Flash BIOS. The check allows you to select the appropriate writing program for the BIOS, with the help of which a special Read Intelligent Identifier command is loaded. The command is also used by the procedures for modifying ESCD and DMI blocks, which can be overwritten both during boot and after it - when applications access the Plug and Play or DMI functions.

BIOS code executed in a work session will be decoded and written to the Run-time area (F000h).

Programming chipset registers

12 Perform a chain of CMOS tests. The RTC clock is set to power mode. CMOS cells are subsequently used to store intermediate results during the initialization procedure. In particular, cells are loaded with default values

14 Perform early chipset initialization. At the first stage, resources that are not available to the motherboard developer are programmed. At the second stage, the values changed using the MODBIN utility are loaded into the chipset registers. Fine-tuning of RAM and PCI devices becomes possible

16 Early initialization of the system clock - setting to default values

18 Determination of processor parameters: manufacturer, family, generation, determination of the type and size of L1 and L2 cache, SMI type. Performing the function of the CPUID command (codes and architecture of processors from different manufacturers differ).

Checking processor registers, measuring processor core clock speed. After executing the function, the result is placed in a 128-bit word formed by the register cells of the central processor - EAX + EBX + ECX + EDX. To decrypt the value of the cache being used, the code is shifted and moved to the AL register

	Initialization of the interrupt vector table (volume 1,024 bytes, 256 types
	interrupts). At this stage, the types for 32 vectors are established (INT 00h-
	INT 1Fh), indicating BIOS procedures.
	Performing checks to ensure Y2K compliance
	Checking CMOS checksum and supply voltage compliance
	battery nominal. If errors are detected, the values are set according to
	defaults set by the motherboard manufacturer

At this stage, receiving scan codes from the keyboard and processing them by the 8742 controller and processor is impossible, since interrupts are disabled, the BIOS data area is not prepared, and the keyboard is not initialized. Setup BIOS settings must not conflict with the execution of the POST sequence

21 Initializing the Hardware Power Management system for laptops.

Formation of a table of physical parameters, a structure for servicing autonomous battery power, energy-saving functions when operating hard drives, as well as operations for saving a RAM image on a disk

23 Math coprocessor detection.

Checking the number of cylinders - 40 or 80, as well as the type of floppy disk installed.

Perform early chipset initialization.

Preparing a BIOS resource map intended for further installation of Plug and Play devices, as well as airborne devices on the PCI bus

24 Processors of the Intel P6 and P7 generations provide the ability to organize access to microprogram memory, which contains algorithms for executing each machine command. At this stage, changes can be made to the firmware microcode to modernize the algorithms or introduce new microcodes designed for new machine instructions. The microcode update procedure is as follows.

Using the CPUID command, the processor is identified and its parameters are determined - Type, Family, Model and Stepping.

The required block of 2,048 bytes is read from the microcode update module stored in the BIOS and unpacked not into RAM, but into SM RAM.

The processor microcode is updated.

Some Intel processors require additional identification. The resource distribution map is being updated

Plug and Play devices are initialized. Information about resources requested by Plug and Play devices is updated based on scanning data from CMOS, BIOS extensions located on the expansion buses, as well as information stored in the ESCD data block. Writing data to ESCD is deferred until the final stage of POST execution

25 Early PCI initialization. Enumeration of devices on the bus. Assignment of RAM and airborne resources.

Search for a video system device, BIOS extensions and write information to area C000:0h (segment address in the CS register: offset address in the IP register)

26 Configuring the logic that serves the Vendor Identification lines.

Completes system clock initialization. Disable synchronization of unused DIMM and PCI slots.

Initialization of the voltage and temperature monitoring system, performed according to the type of motherboard

27 Interrupt enable INT 09h. Re-initialization of the keyboard controller based on new data (interrupt vector table, chipset initialization).

For the BIOS, a 16-character input buffer is formed and a memory area is set for full operation

29 Programming MTRR registers of the P6 generation processor, as well as initializing the APIC controller of Pentium processors.

	Programming the chipset (such as an IDE controller) according to
	with settings in CMOS.
	Measuring the internal processor frequency.
	Calling the video system BIOS extension
	Initializing the multilingual module.
	Sending data to be displayed on the display screen (Award screen saver, type
	processor and its speed)
	Super I/O Chip Programming
	Checking the masking bits of interrupt controller channel 1 (compatible

40 Checking the masking bits of channel 2 of the interrupt controller (compatible with IC 8259)

	Checking the functioning of the interrupt controller (compatible with IC 8259)
	Calculate total memory by checking each double word in each 64 KB page.
	Recording a program designed to test AMD family processors
	Programming MTRR registers of the Syrix family processor. Initialization
	L2 cache of P6 generation processors, as well as APIC initialization for P6
	USB bus initialization
	Check all memory, clear extended memory

55 For a multiprocessor platform, the number of processors is displayed

57 Displays the Plug and Play logo screen. Early provisioning of Plug and Play devices

59 Activating the anti-virus protection resource - the integrated anti-virus tool Trend Anti-Virus

60 Stage allowing you to load the Setup program.

Before this POST stage you must have time to press the appropriate key

65 Initializing a PS/2 computer mouse

67 Preparing information for the address space intended for the call function: INT 15h (contents of register AX=E820h)

	Enabling L2 cache
	Programming chipset registers in accordance with the elements described
	in Setup and in the autoconfiguration table
	Assign resources to all Plug and Play devices.
	Automatic COM port allocation for integrated devices
	if the Setup option is set to “AUTO”
	Initializing the floppy disk controller.
	Additional configuration of floppy disk registers

73 Optional BIOS update utility input function AWDFLASH.EXE if it is on a floppy disk and the key combination is selected

75 Detection and installation of all IDE devices: hard drives, LS-120, ZIP, CD-R/RW, DVD, etc.

If an error is detected, a corresponding message is displayed and the program waits for a keystroke.

If no error is detected or a key is pressed , POST execution continues.

Cleaning the EPA or Manufacturer Logo Screen Saver

82 Depending on the type of chipset and motherboard, an area is allocated in RAM for power management.

The ESCD table is updated with the latest changes related to power management.

After removing the splash screen with the EPA logo, the video mode is restored. Request a password, if provided by CMOS settings

83 Recovering data from a temporary storage stack in CMOS

84 Displays the message “Initializing Plugand Play Cards...” about previously detected Plug and Play devices and parameters

85 USB initialization completed.

Determining boot order from SCSI hard drives

87 Switching the video system to text mode.

Construction of SYSID tables in the DNI area according to the “System Management BIOS” specification.

To serve network devices, a UUID (Universal Unique ID) is created, as well as an identifier for booting from Fire Wire IEEE 1394 devices

At this stage, all basic initialization procedures have been completed. Preparations are being made for loading the operating system, the tables necessary for this are compiled, arrays and structures are formed

89 If the Setup program allows the use of the ACPI protocol, the corresponding tables are inserted into the upper 4 GB address space

	Scanning in the PCI space for BIOS extensions designed for
	implementation of the AOL (Alert On LAN) protocol. Initializing AOL Tools
	Allowing the use of logical means to support unmasked
	NMI interrupts.
	Enable the use of RAM module parity
	For PS/2 mouse hot plugging, IRQ 12 is allowed.
	IRQ 11 line maintenance, normalization of line noise parameters
	interrupt requests

91 Preparing conditions for servicing hard drives in Power Management mode. Operations of this type (Suspend to RAM) can be implemented in a working session of the operating system.

Setting BIOS variables that store the base addresses of serial and parallel ports that host BIOS expansion programs

93 Preparing to save information about boot device partitions

94 If Setup is provided, the L2 cache is enabled. The Boot Up Speed parameter is programmed.

Completing initialization of the chipset and power management system.

Removing the BIOS startup screen, a resource distribution table is displayed on the monitor screen.

Configuring registers for AMD K6 family processors. The final update of the registers of the Intel P6 family of processors.

Final initialization of the Remote Pre Boot subsystem

95 Setting the automatic transition to winter/summer time Daylight Saving.

Programming the keyboard controller for the number of keystrokes per second and the wait time before entering auto-repeat mode.

Reading keyboard KBD ID.

For a 101-key keyboard, the NumLock flag is set according to the CMOS information

96 Saving information about boot device partitions.

In multiprocessor systems, the final configuration of the system is performed, service tables and fields used in the working session of the operating system are formed.

Configuring registers for Cyrix family processors.

Filling and updating the ESCD table in accordance with the state of the Power Management system of Plug and Play and ATAPI devices.

Adjustment of CMOS in accordance with the requirements of the Y2K protocol.

Setting the system clock counter DOS Time in accordance with the RTC CMOS readings. The time value from the “hours:minutes:seconds” format is recalculated

in clock cycles (time intervals of pulse repetition) of the 18.2 Hz interval timer and is recorded in the BIOS variable area - DOS Time.

Saving boot device partitions for future use by integrated antivirus tools Trend Anti-Virus and Paragon Anti-Virus Protection.

Enable the use of L1 cache.

A sound signal for the end of POST is generated on the system unit speaker. Building and saving the MSIRQ table.

Preparing to boot the operating system

FF Transfer control to the initial sector loader program BOOT. Performing BIOS INT 19h interrupt.

The called subroutine allows (in accordance with the BIOS Features Set Up menu option in the Setup program) to poll boot devices to search for the boot sector. To load information from the sector Cylinder: 0, Head: 0, Sector:

1 is read at address 07C0:0000h, after which control of the FAR JMP command is transferred to the beginning of this block

Executing a program written in the boot sector

NOTE.

ECC(Error Correcting Code) — error correction code used in RAM modules, contributing increasing PC fault tolerance. ECC allows error correction in one bit and detection in two bits. Therefore, a computer whose memory uses such codes can operate without interruption in the event of an error in one bit, and the data will not be distorted

BBSS(Boot Block Specification Signature) - Boot block specification signature label.

SMI(System Management Interrupt) - Hardware, integrated into the processor, designed to control power consumption. A high priority interrupt is used to service these components.

Y2K— requirements, requirements for commercial computer system products for ensuring interoperability, functionality and other parameters that occurred before and after 2000.

DMI(Desktop Management Interface) - protocol, allowing for interaction software with motherboard components.

MTRR(Memory Type Range Registers) - generation processor registers P6 And P7, in which Data is entered that describes the properties of memory areas and determines the type of memory caching.

APIC ( Advanced Programmable Interruption Controller) - advanced programmable interrupt controller, included in the chipset. Processor generation P6 Also has a similar controller for multiprocessor applications.

MSIRQ(Microsoft IRQ Routing Map) - table cards distribution interrupts, standardized by Microsoft.

SM RAM(System Management RAM) - one of the names for random access register memory small capacity provided in the processor architecture, starting with Pentium Pro and higher, intended for storing service data.

If each process fails to complete adequately, the algorithm switches to special case processing and POST BIOS Medallion generates the codes noted below:

POST-codesspecialcasesAward BIOS V 6.0 Medallion

System Events codes

Code activated when servicing APM or ACPI components (Power Management Debug codes)

	Energy saving with +12 V supply voltage cut-off
	Switching to operating mode with minimal power consumption
	Interrupt to exit power saving mode by event
	Switching the processor into power saving mode by reducing its clock speed

	Switching to partial power saving mode using ACPI technology
	Using the SMI Component to Enter Power Saving Mode
	Putting the processor into power saving mode using APM technology
	Switching the system into power saving mode using APM technology
	Putting the system into full power saving mode

Message about fatal errors during operations (System Error codes)

	ECC code processing error
	Hard drive error when returning from power saving mode
	Data mismatch when writing to and reading from segment F000h

To reduce the time it takes to complete the POST Award BIOS test program, you can use the Quick Power On Self Test option, which can be found in the Setup program. In this case, a modified version of the Award Software test is launched, which, unlike the full version of the program, runs quickly.

POST AMI BIOS 8 V1.4 checkpoint codes

Understanding the Breakpoint Code Display

To display POST AMI BIOS checkpoints, POST Diagnostic Cards, indicators on system boards, and displays control AMI BIOS Checkpoint Display.

The display is a line of code in the lower right corner of the monitor screen that appears during POST.

The disadvantage of using the checkpoint code display is that it cannot be used when the video system is turned off.

Purpose of the Device Provisioning Manager

During various periods of POST testing, control is transferred to a special program DIM device initialization manager(Device Initialization Manager).

This program receives control from the BIOS if it is necessary to check the system or local buses of the computer. There are several POST checkpoints designed to run this program.

2Ah initialization of devices on the system bus.

38h initialization of IPL devices.

39h indication of errors during bus initialization.

95h initialization of buses controlled by BIOS extensions.

DEh - RAM configuration error.

DFh - RAM configuration error.

Messages generated by the DIM are also output to diagnostic port 80h and stored in the data word while the test is running.

The word in which the marked information is stored contains the low byte, which matches the system POST code. The high byte is divided into two tetrads. Below is a description of the codes loaded into notebooks.

Fields of the senior tetrad.

Initialization of all devices on the buses of interest is prohibited.

Initialize static devices on the buses of interest.

Initialization of information output devices on the buses of interest.

Initialization of information input devices on the buses of interest.

Initialize system load (IPL) devices on the buses of interest.

Initialize general purpose devices on the buses of interest.

Error messages for the tires of interest.

Initialization of devices controlled by BIOS extensions (for all buses).

Initialize BIOS boot extensions that comply with the BIOS Boot Specification (for all buses).

Junior tetrad.

System initialization procedures (DIM).

Buses for connecting integrated system devices.

ISA bus Plug and Play.

PCMCIA bus.

If a RAM configuration error is detected, a cyclic sequence of codes DEh, DFh and configuration checkpoints is output to the diagnostic port, which can take the following values.

00 No RAM detected.

01 different types of DIMMs are installed.

02 Reading from the SPD (Serial Presence Detect) node of the DIMM failed.

03 DIMM cannot be used at this frequency.

04 DIMM cannot be used in this system.

05 error in the low memory page.

Analysis of computer errors using a diagnostic card (POST card)

1. Introduction
2. General description of POST card

4. Error code table
5. Description of sound signals
6. Reset a forgotten BIOS password

Introduction

The card is called POST (Power On Self Test - self-test card). Displays error codes when the operating system cannot boot or there is no image on the screen or no BIOS sounds.

When power is applied, the BIOS performs an accurate test of the circuit, memory, keyboard, video card, hard drive, then analyzes the system configuration. After the basic input/output system is initialized, the operating system loads.

The diagnostic card will not display data in the following cases:
1. The card is inserted into the motherboard without a CPU.
2. When the RST LED is lit.

General description of POST card

Codes on the map are displayed in a certain sequence

The code may not be defined

For different BIOS manufacturers (AMI, Award, Phoenix), the meaning of the codes is different. (BIOS manufacturer definition)

The card can be connected to PCI and ISA slots. Typically the codes start from "00" to "FF" on the PCI slot. On some motherboards the code may stop at "38"

On motherboards, BIOS error codes are constantly updated, so they may not be listed in the table.

Some POST cards may be missing some LEDs.

Description of luminous diodes:

Light-emitting diode	Type	Description
RUN	Flicker	If the LED is on, the motherboard is turned on, it doesn't matter what codes are running
CLK	BUS CLOCK	Lights up when power is supplied to the motherboard (usually without a processor)
BIOS	Read BIOS	The LED turns on and off when power is supplied to the motherboard, when the processor is reading the BIOS
IRDY	The manager is ready	LED turns on and off when there is a message
O.S.C.	Flashing	Lights up when power is supplied to the motherboard, or if not, then the oscillating circuit crystal is broken
FRAME	Frame period	It's on all the time. Turns on and off when there is a message
RST	Reset	Lights up for half a second when you press the power or reset button. If the power is on, then it is worth checking RESET (shorted or broken).
12V	Power	Lights up once when turned on, power is supplied, if it doesn’t light up it means a short circuit on the motherboard or no 12V.
-12V	Nutrition	Same as "12V"
5V	Nutrition	Same as "12V"
-5V	Nutrition	Same as "12V" (-5V only for ISA slot)
3V3	Nutrition	Lights up when power is applied (PCI only), where there is 3.3V. If there is no standby voltage of 3.3V on the motherboard, it does not light up

Error Code Table

Code	Award	AMI	Phoenix4.0/Tendy3000
00		Code copying to specific areas is done/Passing control to INT 19h boot loader next.
01	Processor Test 1, Processor status (1FLAGS) verification. Test the following processor status flags: carry, zero, sign, overflow. The BIOS sets each flag, verifies they are set, then turns each flag off and verifies it is off.		CPU is testing the register inside or failed, please change the CPU and check it.
02	Test All CPU Registers Except SS, SP, and BP with Data FF and 00		Verify Real Mode
03	Disable NMI, PIE, AIE, UEI, SQWV Disable video, parity checking, DMA Reset math coprocessor Clear all page registers, CMOS shutdown byte Initialize timer 0, 1, and2, including set EISA timer to a known state Initialize DMA controllers 0 and 1 Initialize interrupt controllers 0 and 1 Initialize EISA extended registers	Disable NMI, PIE, AIE, UEI, SQThe NMI is disabled. Next, checking for a soft reset or a power on condition	Disable Non-Mask-able interrupt (NMI)
04	RAM must be periodically refreshed to keep the memory from decaying. This refresh function is working properly		Get CPU type
05	Keyboard Controller initialization	The BIOS stack has been built. Next, disabling cache memory.	DMA initialization in progress or failure
06	Reserved	Uncompressing the POST code next.	Initialized system hardware
07	Verifies CMOS is Working Correctly, Detects Bad Battery	Next, initializing the CPU data area	Disable shadow and execute code from the ROM
08	Early chip set initialization Memory presence test OEM chip set routines Clear low 64K memory Test first 64K memory	The CMOS checksum calculation is	Initialize chipset with with initial POST values
09	Cyrix CPU initialization Cach initialization		Set IN POST flag
0A	Initialize first 120 interrupt vectors with SPURIOUS-INT-HDLR and initialize INT 00h-1Fh according to INT-TBL	The CMOS checksum calculation is done. Linitializing the CMOS status register for date and time next	Initialize CPU registers
0B	Test CMOS RAM Checksum. If bad, or INS Key Pressed, Load Defaults	The CMOS status register is initialized. Next. Performing any require initialization before the keyboard BAT command is issued	Enable CPU cache
0C	Detect Type of Keyboard Controller and Set NUM LOCK Status	The keyboard controller input butter is free Next, issuing the BAT command to the keyboard controller	Initialize caches to initial POST values
0D	Detect CPU Clock Read CMOS location 14h to find out type of video in use Detect and initialize video adapter
0E	Test Video Memory, write sign-on message to screen Setup shadow RAM? Enable shadew according to setup	The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test	Initialize I/O component
0F	Test DMA Cont. 0; BIOS Checksum Test Keyboard Detect and initialization	The initialization after the keyboard controller BAT command test is done. The keyboard command byte is written next	Initialization of the local bus IDE
10	Test DMA Controller 1	Test DMA The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 Blocking and unblocking command	Initialize Power Management
11	Test DMA Page Registers	Next, checking if "End" or "Ins" keys were pressed during power on. Initializing CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the "End" key was pressed
12	Reserved	Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2	Restore CPU control word during warm boot
13	Reserved	The video display has been disabled. Port B has been initialized. Next, initializing the chipset	initialize PCI Bus Mastering devices
14	Test 8254 Timer 0 Counter 2	The 8254 timer test will begin next
15	Verify 8259 Channel 1 interrupts by Turning Off and On the interrupt Lines
16	Verify 8259 Channel 2 interrupts by Turning Off and On the interrupt Lines		BIOS ROM checksum
17	Turn Off interrupts Then Verify No Interrupt Msk Register is On		Initialize cache before memory Auto size
18	Force an interrupt and Verify the interrupt and Verify the interrupt Occurred		8254 timer initialization
19	Test Stuck NMI Bits; Verify NMI Can Be Cited		The 8254 timer test is over. Starting the memory refresh test next
1A	Display CPU clock	The memory refresh line is toggling. Checking the 15 seconds on/off time next
1B	Reserved
1C	Reserved		Reset Programmable interrupt Controller
1D	Reserved
1E	Reserved
1F	If EISA non-volatile memory checksum is good, execute EISA initialization If not, execute ISA tests an clear EISA mode flag Test EISA configuration memory Integrity (checksum & communication interface)
20	Initialize Slot O (System Board)		Test DRAM refresh
21	Initialize Slot 1
22	Initialize Slot 2		Test 8742 Keyboard Controller
23	Initialize Slot 3	Reading the 8042 input port and disabling the MEGAKEY Green PC feature next. Making the BIOS code segment writable and performing any necessary configuration before initializing the interrupt vectors
24	Initialize Slot 4	The configuration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin	Set ES segment register to 4Gb
25	Initialize Slot 5	Interrupt vector initialization is done. Clearing the password if the POST DIAG awitch is on
26	1. test the exceptional situation of protected of protected mode, check the memory of cpu and mainboard. 2. no fatal trouble, VGA displayed normally. If nonfateful trouble occurred, then display error message in VGA otherwise boot operating system, and code "26" is OK code, no any other codes to display	1. read/write input, output port of 8042 keyboard; ready for revolve mode, continue to get ready for initialization of all data, check the 8042 chips on mainboard. 2. refer to the left	1. enable A20 adress line, check the A20 pins of memory controlling chips, and check circuit, correlated to pins, in memory slot, may be A20 pin and memory pins are not in contact, or memory A20 pins bad. 2. refer to the left
27	Initialize Slot 7	Any initialization before setting the video mode will be done next
28	Initialize Slot 8	Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next	Auto size DRAM
29	Initialize Slot 9		Initialize POST Memory Manager
2A	Initialize Slot 10	Initializing the different bus system, static, and output devices, if present	Clear 512 KB base RAM
2B	Initialize Slot 11	Passing control to the video ROM to perform any required configuration before the video ROM test
2C	Initialize Slot 12	All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it	RAM failure on address line xxx*
2D	Initialize Slot 13	The video ROM has returned has returned control to BIOS POST Performing any required processing after the video ROM had control
2E	Initialize Slot 14	Completed pest-video ROM test processing. If the EGA/VGA controller is not found, performing the display memory Read/write test next	RAM failure on data bits Xxxx* of low byte of memory bus
2F	Initialize Slot 15	The EGA/VGA controller was not found. The display memory read/write test is about to begin	Enable cache before system BIOS shadow
30	Size Base Memory From 256K to 640K and Extended Memory Above 1MB	The display memory read/write test passed. Look for retrace checking next
31	Test Base Memory From 256K to 640K and Extended Memory Above 1MB	The display memory read/write test or retrace checking failed. Performing the alternate display memory read/write test next
32	If EISA Mode, Test EISA Memory Found in Slots initialization	The alternate display memory read/write test passed. Looking for alternate display retrace checking next	Test CPU Bus-clock frequency
33	Reserved		Initialize Phoenix Dispatch manager
34	Reserved	Video display checking is over. Setting the display mode next
35	Reserved
36	Reserved		Warm start and shut down
37	Reserved	The display mode is set. Displaying the power on message next
38	Reserved	Initializing the bus input, IPL, general device next, if present	Shadow system BIOS ROM
39	Reserved	Displaying bus initialization error messages
3A	Reserved	The new cursor position has been read and saved. Displaying the Hit "Del" message next	Auto size cache
3B	Reserved	The Hit "Del" message is displayed. The protected mode memory test is about to start
3C	Setup Enabled		Advanced configuration of chipset registers
3D	Detect if mouse is present, initialize mouse, install interrupt vectors
3E	Initialize cache controller
3F	Reserved
40	Display virus protect. Disable or Enable	Preparing the descriptor tables next
41	Initialize Floppy Disk Drive Controller and any drives		Initialize extended memory for RomPilot
42	Initialize Hard Drive Controller and any drives	The descriptor tables are prepared. Enteling protected mode for the memory test next	Initialize interrupt vectors
43	Detect and initialize Serial & Parallel Ports and Game Port	Entered protected mode. Enabling interrupts for diagnostics mode next
44	Reserved	Interrupts enabled if the diagnostics switch is on. Initializing data to check memory wraparound at 0:0 next
45	Detect and initialize math coprocessor	Data initialized. Checking for memory wraparound at 0: 0 and finding the total system memory size next	POST device initialization
46	Reserved	The memory wraparound test is done. Memory size calculation has been done. Writing patterns to tset memory next	Check ROM copyright notice
47	Reserved	The memory pattern has been to extended memory. Writing patterns to the base 640 KB memory	Initialize 120 support
48	Reserved	Patterns written in base memory. Determining the amount of memory below 1MB next
49	Reserved	The amount of memory below 1MB has been found and verified. Determining the amount of memory above 1 MB memory next
4A	Reserved
4B	Reserved	The amount of memory above 1MB has been found and verified. Checking for a soft reset and clearing the memory below 1MB for the soft reset next. If this is a power on situation, going to checkpoint 4Eh next	QuletBoot start (optional)
4C	Reserved	The memory below 1MB has been cleared via a soft reset. Clearing the memory above 1MB next	Shadow video BIOS ROM
4D	Reserved	The memory above 1MB has been cleared via a soft reset. Saving the memory size next. Going to checkpoint 52h next
4E	Reboot if Manufacturing Mode; if not, Display Messages and Enter Setup	The memory test started, but not as the result of a soft reset. Displaying the first 64KB memory size next	Display BIOS copyright notice
4F	Ask Password Security (Optional)	The memory size display has started. The display is updated during the memory test. Performing the sequential and random memory test next	Initialize MultiBoot
50	Write All CMOS Values Back to RAM and Clear	The memory below 1MB has been tested and initialized. Adjusting the displayed memory size fot relocation and shadowing next	Display CPU type and speed
51	Enable Parity Checker. Enable NMI, Enable Cache Before Boot	The memory size display was adjusted for relocation and shadowing. Testing the memory above 1MB next	Initialize EISA board
52	Initialize Option ROMs from C8000h to EFFFFh or if FSCAN Enabled to F7FFFh	The memory above 1MB has been tested and initialized. Saving the memory size information next	Test keyboard
53	Initialize Time Value in 40h: BIOS Area	The memory size information and the CPU registers are saved. Entering real mode next
54		Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, parity, and the NMI next	Set key click if enabled
55
56			Enable USB devices
57		The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next
58		The memory size was adjusted for relocation and shadowing. Clearing the Hit "DEL" message next
59		The Hit "DEL" message is cleared. The "WAIT..." message is displayed. Starting the DMA and interrupt controller test next	Initialize POST display service
5A			Display prompt Press F2 to enter SETUP
5B			Disable CPU cache
5C			Test RAM betweeb 512 and 640 kB
60	Setup virus protection (boot sector protection) functionality according to setup setting	The DMA page register test passed. Performing the DMA Controller 1 base register test next	Test extended memory
61	Try to turn on level 2 cach (if L2 cach already turned on in post 3D, this part will be skipped) Sat the boot up speed according to setup setting Last chance for chipset initialization Last chance for power management initialization (Green BIOS Only) Show the system configuration table
62	Set up the NUM lock. According to setup values Programm the NUM lock. Typematic rate & typematic speed according to setup setting	The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next	Test extended memory address lines
63	If there is any changes in the hardware configuration. Update the ESCD information (PnP BIOS only) Clear memory that have been used Boot system via INT 19h
64			Jump to UserPatch1
65		The DMA controller 2 base register test passed. Programming DMA controller 1 and 2 next
66		Completed programming DMA controllers 1 and 2 initializing the 8259 interrupt controller next	Configure advanced cache registers
67		Completed 8259 interrupt controller initialization	Initialize Multi Processor APIC
68
69			Setup System Management Mode (SSM) area
6A			Display external L2 cache size
6B			Load custom defaults (optional)
6C			Display shadow-area message
6E			Display possible high address for UMB recovery
6F
70			Display error message
71
72
76			Check for keyboard errors
7C			Set up hardware interrupt vectors
7D			Initialize intelligent System Monitoring
7E			Initialize coprocessor if present
7F		Extended NMI source enabling is in progress
80		The keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing the keyboard reset command next	Disable onboard Super I/O ports and IRQs
81		A keyboard reset error or stuck key was found. Issuing the keyboard controller interface test command next	Late POST device initialization
82		The keyboard controller interface test completed. Writing the command byte and initializing the circular buffer next	Detect and install external RS232 ports
83		The command byte was written and global data initialization has completed. Checking for a locked key next	Configure non-MCD IDE controllers
84		Locked key checking is over. Checking for a memory size mismatch with CMOS RAM data next
85		The memory size check is done. Displaying a soft error and checking for a password or bypassing WINBIOS Setup next	Initialize PC-compatible PnP ISA devices
86		The password was checked. Performing any required programming before WINBIOS Setup next
87		The programming before WINBIOS Setup has completed Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next	Configure Motherboard Configurable Devices (optional)
88		Returned from WINBIOS Setup end cleared the screen. Performing any necessary programming after WINBIOS Setup next	Initialize BIOS Data Area
89		The programming after WINBIOS Setup has completed. Displaying the power on screen message next	Enable Non-Maskable interrupts (NMis)
8A			Initialize Extended BIOS Data Area
8B		The first screen message has been displayed. The "WAIT..." message is displayed. Performing the PS/2 mouse check and extended BIOS data area allocation check next	Test and initialize PS/2 mouse
8C		Programming the WINBIOS Setup options next	Initialize floppy controller
8D		The WINBIOS Setup options are programmed. Resetting the hard disk controller next
8E		The hard disk controller has been reset. Configuring the floppy drive controller next
8F			Determine number of ATA drives (optional)
90			Initialize hard-disk controllers
91		The floppy drive controller has been configured. Figuring the hard disk drive controller next	Initialize local-bus hard-disk controllers
92			Jump to UserPatch2
93			Build MPTABLE for multi-processor board
95		Initializing bus adapter ROMs from C8000h through D8000	Install CD ROM for boot
96		Initializing before passing control to the adapter ROM at C800
97		Initialization before the C800 adapter ROM gains control has completed. The adapter ROM check is next	Fix up Multi Processor table
98		The adapter ROM had control and now returned control to BIOS POST. Performing any required processing after the option ROM returned controlA	Search for option ROMs. One long, two short beeps on checksum failure
99		Any initialization required after the option ROM test has completed. Configuring the timer data area and printer base address next	Check for SMART Drive (optional)
9A		Set the timer and printer base address. Setting the RS-232 base address next	Shadow option ROMs
9B		Returned after setting the RS-232 base address. Performing any required initialization before the coprocessor test next
9C		Required initialization before the Coprocessor test is over. Initializing the Coprocessor next	Set up Power Management
9D		Coprocessor initialized Performing any required initialization after the Coprocessor test next	Initialize security engine (optional)
9E		Initialization after the Coprocessor test is complete. Checking the extended keyboard, keyboard ID, and NumLock key next. Issuing the keyboard ID command next	Enable hardware interrupts
9F			Determine number of ATA and SCSI drivers
A0			Set time of day
A1			Check key lock
A2		Displaying any soft error next
A3		The soft error display has completed. Setting the keyboard typmatic rate next
A4		The keyboard typematic rate is set. Programming the memory wait states next	Initialize typematic rate
A5		Memory wait state programming is over. Clearing the screen and enabling parity and the NMI next
A7		NMI and parity enabled. Performing any initialization required before passing control to the adapter ROM at E000 next
A8		Initialization before passing control to the adapter ROM at E000h completed. Passing control to the adapter ROM at E000h next	Erase F2 prompt
A9		Returned from adapter ROM at E000h control. Performing any initialization required after the E000 option ROM had control next
A.A.		Initialization after E000 option ROM control has completed. Displaying the system configuration next	Scan for F2 key stroke
AB		Uncompressing the DMI data and executing DMI POST initialization next
A.C.			Enter SETUP
A.E.			Clear boot flag
B0	If interrupts Occurs in protected mode	The system configuration is displayed	Check for errors
B1	If unmasked NMI Occurs. Display Press F1 to Disable NMI, F2 Reboot	Copying any code to specific areas	Inform RomPilot about the end of POST
B2			POST prepare done to boot operating system
B3
B4			1 One short beep before boot
B5			Terminate Quiet Boot (optional)
B6			Check password (optional)
B7			Initialize ACPI BIOS
B8
B9			Prepare Boot
B.A.			Initialize SMBIOS
BB			Initialize PnP Option ROMs
B.C.			Clear parity checkers
BD			Display MultiBoot menu
BE	Program chipset registers with power on BIOS defaults		Clear screen (optional)
B.F.	Program the rest of the chipset "s value according to setup (later setup value program) If auto configuration is anabled, programmed the chipset with predefined values in the MODBINable Auto Table		Check virus and backup reminders
C0	Turn off OEM specific cach, shadow Initialize standard devices with default values: DMA controller (8237); Programmable interrupt Controller (8259); Programmable interval Timer (8254); RTC chip		Try to boot with INT 19
C1	OEM Specific-Test to size On-Board memory		Initialize POST error manager (PEM)
C2			Initialize error logging
C3	Test the first 256K DRAM Expand the compressed codes into temporary DRAM area including the compressed system BIOS & Option ROMs		Initialize error display function
C4			Initialize system error handler
C5	OEM Specific-Early Shadow Enable for fast boot		PnPnd dual CMOS (optional)
C6	External Cache Size Detection		Initialize note dock (optional)
C7			Initialize note dock late
C8			Force check (optional)
C9			Extended checksum (optional)
C.A.			Redirect int 15h to enable remote keyboard
C.B.			Redirect int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk
CC			Redirect int 10h to enable remote serial video
CD			Re-map I/O and memory for PCMCIA
C.E.			Initialize digitizer and display message
D0		The NMI is disable. Power on delay is starting. Next, the initialization code checksum will be verified
D1		Initializing the DMA controller, performing the keyboard controller BAT test, starting memory refresh, and entering 4GB flat mode next
D2			Unknown interrupt
D3		Starting memory sizing next
D4		Returning to real mode. Executing any OEM patches and setting the next stack
D5		Passing control to the uncompressed code in shadow RAM at E000: 0000h. The initialization code is copied to segment 0 and control will be transferred to segment 0
D6		Control is in segment 0 Next, checking if "Ctrl" "Home" was pressed and verifying the system BIOS checksum. If either "Ctrl" "Home" was pressed or the system BIOS checksum is bad, next will go to checkpoint code E0h. Otherwise, going to checkpoint code D7h
E0		The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test	Initialize the chipset
E1	E1 Setup-Page E1	Initializing the interrupt vector table next	Initialize the bridge
E2	E2 Setup-Page E2	Initializing the DMA and interrupt controllers next	Initialize the CPU
E3	E3 Setup-Page E3		Initialize system timer
E4	E4 Setup-Page E4		Initialize system I/O
E5	E5 Setup-Page E5		Check force recovery boot
E6	E6 Setup-Page E6	Enabling the floppy drive controller and Timer IRQs. Enabling internal cache memory	Checksum BIOS ROM
E7	E7 Setup-Page E7		Go to BIOS
E8	E8 Setup-Page E8		Set Huge Segment
E9	E9 Setup-Page E9		Initialize Multi Processor
E.A.	EA Setup-Page EA		Initialize OEM special code
E.B.	EB Setup-Page EB		Initialize PIC and DMA
E.C.	EC Setup-Page EC		Initialize Memory type
ED	ED Setup-Page ED	Initializing the floppy drive	Initialize Memory size
E.E.	EE Setup-Page EE	Looking for a floppy diskette in drive A: Reading the first sector of the diskette	Shadow boot block
EF	EF Setup-Page EF	A read error occurred while reading the floppy drive in drive A:	System memory test
F0		Next, searching for the AMIBOOT.ROM file in the root directory	Initialize interrupt vectors
F1		The AMIBOOT.ROM file is not in the root directory	Initialize Run Time Clock
F2		Next, reading and analyzing the floppy diskette FAT to find the clusters occupied by the AMIBOOT.ROM file	Initialize video
F3		Next, reading the AMIBOOT.ROM file, cluster by cluster	Initialize System Management Manager
F4		The AMIBOOT.ROM file is not the correct size	Output one beep
F5		Next, disabling internal cache memory	Clear Huge Segment
F6			Boot to mini DOS
F7			Boot to full DOS
FB		Next, detecting the type of flash ROM
F.C.		Next, erasing the flash ROM
FD		Next, programming the flash ROM
FF		Flash ROM programming was successful. Next, restarting the system BIOS

Description of sound signals

AMI BIOS Fatal Errors

1 beep	DRAM Refresh Failure. Try reseating the memory first. If the error still occurs, replace the memory with known good chips.
2 beeps	Parity error in first 64K RAM. Try reseating the memory first. If the error still occurs, replace the memory with known good chips
3 beeps	Base 64K RAM Failure. Try reseating the memory first. If the error still occurs, replace the memory with known good chips
4 beeps	System timer failure
5 beeps	Process failure
6 beeps	Keyboard controller 8042-Gate A20 Error. Try reseating the keyboard controller chip. If the error still occurs, replace the keyboard chip. If the error persists, check parts of the system relating to the keyboard, e.g. try another keyboard, check to see if the system has a keyboard fuse
7 beeps	Processor, Virtual Mode Exception Interrupt Error
8 beeps	Display memory Read/Write test failure (non-fatal). Replace the video card or the memory on the video card
9 beeps	ROM BIOS Checksum (32KB at F800:0) Failed. It is not likely that this error can be corrected by reseating the chips. Consult the motherboard supplier or an AMI product distributor for replacement part(s)
10 beeps	CMOS shutdown register read/write error
11 beeps	Cache memory error

AMI BIOS beep codes (not fatal errors)

2 short	POST Failure-one or more of the hardware tests has failed
1 long 2 short	An error was encountered in the video BIOS ROM, or a horizontal retrace failure has been encountered
1 long 3 short	Conventional/Extended memory failure
1 long 8 short	Display/Retrace test failed

Award BIOS beep codes

1 short	No error during POST
2 short	Any Non-fatal error, enter CMOS SETUP to reset
1 long 1 short	RAM or motherboard error
1 long 2 short	Video error, cannot initialize screen to display any information
1 long 3 short	Keyboard controller error
1 long 9 short	Flash RAM/EPROM (which on the motherboard) error. (BIOS error)
long beep	Memory bank is not plugged well, or broken

Phoenix BIOS beep codes

Sound codes	Description/What to check?
1-1-1-3	Verify real mode
1-1-2-1	Get CPU type
1-1-2-3	Initialize system hardware
1-1-3-1	Initialize chipset registers with initial POST values
1-1-3-2	Set in POST flag
1-1-3-3	Initialize CPU registers
1-1-4-1	Initialize cache to mitial POST values
1-1-4-3	Initialize I/O
1-2-1-1	Initialize Power management
1-2-1-2	Load alternate registers with initial POST values
1-2-1-3	Jump to User Patch0
1-2-2-1	Initialize keyboard controller
1-2-2-3	BIOS ROM checksum
1-2-3-1	8254 timer initialization
1-2-3-3	8237 DMA controller initialization
1-2-4-1	Reset programmable interrupt controller
1-3-1-1	Test DRAM refresh
1-3-1-3	Test 8742 keyboard controller
1-3-2-1	Set ES segment to register to 4GB
1-3-3-1	28 Autosize DRAM
1-3-3-3	Clear 512K base RAM
1-3-4-1	Test 512K base address lines
1-3-4-3	Test 512K base memory
1-4-1-3	Test CPU BUS-clock frequency
1-4-2-4	Reinitialize the chipset
1-4-3-1	Shadow system BIOS ROM
1-4-3-2	Reinitialize the cache
1-4-3-3	Autosize cache
1-4-4-1	Configure advanced chipset registers
1-4-4-2	Load alternate registers with CMOS values
2-1-1-1	Set initial CPU speed
2-1-1-3	Initialize interrupt vectors
2-1-2-1	Initialize BIOS interrupts
2-1-2-3	Check ROM copyright notice
2-1-2-4	Initialize manager for PCI options ROMs
2-1-3-1	Check video configuration against CMOS
2-1-3-2	Initialize PCI bus and devices
2-1-3-3	Initialize all video adapters in system
2-1-4-1	Shadow video BIOS ROM
2-1-4-3	Display copyright notice
2-2-1-1	Display CPU type and speed
2-2-1-3	Test keyboard
2-2-2-1	Set key click if enabled
2-2-2-3	56 enable keyboard
2-2-3-1	Test for unexpected interrupts
2-2-3-3	Display prompt "press F2 to enter SETUP"
2-2-4-1	Test RAM between 512 and 640k
2-3-1-1	Test expanded memory
2-3-1-3	Test expanded memory address lines
2-3-2-1	Jump to user patch1
2-3-2-3	Configure advanced cache registers
2-3-3-1	Enable external and CPU caches
2-3-3-3	Display extemal cache size
2-3-4-1	Display shadow massage
2-3-4-3	Display non-disposable segments
2-4-1-1	Display error massages
2-4-1-3	Check for configuration errors
2-4-2-1	Test real-time clock
2-4-2-3	Check for keyboard errors
2-4-4-1	Set up hardware interrupts vectors
2-4-4-3	Test coprocessor of present
3-1-1-1	Display onboard I/O ports
3-1-1-3	Detect and install external Rs232 ports
3-1-2-1	Detect and install external parallel ports
3-1-2-3	Re-initialize onboard I/O ports
3-1-3-1	Initialize BIOS data area
3-1-3-3	Initialize extended BIOS data area
3-1-4-1	Initialize floppy controller
3-2-1-1	Initialize hard-disk controller
3-2-1-2	Initialize local-bus hard-disk controller
3-2-1-3	Jump to userPatch2
3-2-2-1	Disable A20 address line
3-2-2-3	Clear huge ES segment register
3-2-3-1	Search for option ROMs

IBM BIOS beep codes

Sound codes	Description
No beeps	No Power, Loose card or short
1 short beep	Normal POST, computer is ok
2 short beeps	POST error, review screen for error code
continuous beep
Repeating short beep	No power, loose card, or short
One long and one short beep	Motherboard issue
One long and two short beeps	Video (EGA) display circuitry
Three long beeps	Keyboard/keyboard card error
One beep, blank or incorrect display	Video display circuitry

Resetting a forgotten BIOS password

AMI passwords:

Other BIOS:

Phoenix BIOS: phoenix	Megastar: star
Biostar Biostar: Q54arwms	Micron: sldkj754xyzall
Compag: compag	Micronies: dn 04rie
CTX international: CTX_123	Packard Bell: bell9
Dell: Dell	Shuttle: space
Digital Equipment: comprie	Siements Nixdorf: SKY FOX
HP Vectra: hewlpack	Tinys: tiny
IBM: IBM MBIUO sertafu	TMC:BIGO

Reset BIOS password programmatically.

The CMOS ROM can be reset programmatically using the command line with the command debug(Works only up to Windows 7 version, does not work in 8).

Reset Award BIOS password:
C:\>debug
-o 70 34 "Enter"
-o 71 34 "Enter"
-q "Enter"
or
C:\>debug
-o 70 11 "Enter"
-o 71 11 "Enter"
-q "Enter"

Reset AMI BIOS password:
C:\>debug
-o 70 16 "Enter"
-o 71 16 "Enter"
-q "Enter"
or
C:\>debug
-o 70 10 "Enter"
-o 71 0 "Enter"
-q "Enter"

Reset Phoenix BIOS password:
C:\>debug
-o 70 ff "Enter"
-o 71 17 "Enter"
-q "Enter"

What it looks like on the command line:

The BIOS settings will be erased, so the next time the system boots, you may need to change the settings (for example, if your disk startup order is different, then you need to reassign, otherwise the system will not boot).

Hard reset CMOS BIOS with jumper

Turn off your computer completely from the network

Switch the jumper from position 1-2 to position 2-3

Turn on the power, restart the computer

Turn off your computer. Return the jumper to position 1-2

Turn on the computer, BIOS settings should be reset

Usually, completing the first two steps is enough, just return the jumper to its original position. You can simply close the pins with a screwdriver if the jumper is missing. The pins are usually labeled on the motherboard: Clear CMOS, CL_CMOS, CRTC, CCMOS, CL_RTC, Clean CMOS, CMOS ROM Reset. Or you can simply remove the battery.

You can use the universal CMOS De-Animator utility to reset the BIOS settings programmatically. Can save settings to a file and restore them. Download from the official website CMOS De-Animator

And a small sign telling you which keys you can use to enter the BIOS settings:

Decoding POST card codes for "Award BIOS 4.5"

Award BIOS Version 4.51PG

C0 programming the registers of the Host Bridge chip to set the following modes: External Cache is disabled. Copying information read by the processor into External Cache cells is prohibited (all bus cycles are Non Cacheable), and viewing TAGRAM for cache hits (Force Cache Miss) is also prohibited. Internal Cache is disabled. The generation of the KEN# signal by the Host Bridge chip is prohibited; this prevents the processor from caching read data. Before disabling, Internal Cache is cleared by software or hardware. Shadow RAM is prohibited. This causes cycles to access the System BIOS and Additional BIOS location addresses directly to the corresponding ROMs, rather than Shadow RAM. This procedure is written for a specific Chipset. Programming of PIIX resources is carried out: DMA controller, interrupt controller, timer, RTC block. The DMA controller is switched to passive mode, since specific initialization of channels (setting base addresses, block lengths, transmission modes) is not a task of POST, but of programs supporting peripheral devices, which are executed during the working session. The interrupt controller is configured as follows.

Master Controller (IRQ0-IRQ7) :vector interrupt mode, receiving a request on an IRQ edge in accordance with IRQ0=INT8...IRQ7=INT0Fh.
Slave Controller (IRQ8-IRQ15) :vector interrupt mode, receiving a request on an IRQ edge in accordance with IRQ8=INT70h...IRQ15=INT77h.
At this stage, only the interrupt controller is prepared for operation, the interrupts themselves are disabled, and are allowed much later, presumably after a memory test. 31 The timer is configured as follows.
Counter 0: generates IRQ0 requests to count DOS Time, sets the frequency division mode to 65536, resulting in an IRQ0 frequency of 18.2 Hz.
Counter 1: generation of DRAM Refresh requests, the frequency division mode is set to 20, as a result, the interval between regeneration of two DRAM lines is about 15 µS, i.e. 128 cycles are completed in 2 ms.
Counter 2: Used for sound. At this stage, it is simply transferred to a passive state; the parameters of this counter are set when a signal is output to the system speaker.
The Real Time Clock subsystem only needs to be initialized if there is a battery failure. Otherwise, a full CMOS initialization is not performed because this would reset the clock every time it is turned on. If there was no VCC(BAT) failure, only the registers responsible for interaction between the RTC and the processor are initialized, but not the clock itself
C1 By sequential writes and control reads, the memory type, total volume and row placement are determined. The result of this step is to configure the following DRAM controller parameters:memory type (SDRAM, EDO, FPM);mapping information (depending on Socket location);value of the Memory parameter.If the address generated by the processor exceeds Memory , this cycle is sent to PCI. More precise adjustment of DRAM timing parameters is performed later, in accordance with the contents of Setup RAM or SPD
C3 Checking the first 256K DRAM for the Temporary Area organization. Unpacking System BIOS into DRAM, copying Option ROMs into DRAM. This step is performed in preparation for Operation Shadow. The need for a Temporary Area is due to the fact that Shadow RAM blocks assigned to the corresponding ROMs are included in the same address ranges as the ROMs themselves, because of this it is impossible to transfer (unpack) in one step, because the ROM must be read, and write to Shadow RAM. Therefore, first, ROM is mapped to the appropriate range and transferred (unpacked) to the transit buffer Temporary Area, then the Host Bridge is reprogrammed so that Shadow RAM is mapped to the BIOS address area and the code is transferred from the transit buffer to Shadow RAM. At stage C3, the first 256 KB of DRAM are tested, which will later be used as a transit buffer.
The checksums are checked and the presence of the BBSS tag is checked. If the tag is not detected or the checksums do not match, a decision is made that the BIOS firmware is partially damaged. Control is transferred to the FlashROM recovery routine located in the BootBlock. (BootBlock POST Codes)
C5 Executed POST code is moved to Shadow RAM and then executed from Shadow RAM to speed up POST execution.
Shadow RAM is faster than ROM for two reasons: ROM is 8-bit wide, RAM is equal to the processor's local data bus. The access time of used DRAM is significantly less than that of used ROM / Flash ROM
C6 Determining the presence, size and type of External Cache. The presence and parameters of External Cache are determined by writes and control reads using a special algorithm
C8 Checking the integrity of BIOS components located in ROM. If the checksum of the components does not match, it is concluded that the 128 KB area containing the awardext.rom file external to the system BIOS is damaged. Because the system BIOS is stored in the next 128 KB block, some 2 Mbit BIOSes can handle this error gracefully and pass control to the recovery program.
CFDetermining the processor type. The result is placed in CMOS. Since not all RTCs are initialized at this point, a read/write test is performed first.
If for some reason the determination of the CPU type fails, such an error becomes fatal and POST is no longer executed and the system stops.

01 In earlier versions of BIOS, the flags of the characteristics of the result of an arithmetic operation were checked using the following algorithm: the carry (CF), zero (ZF), sign (SF), overflow (OF) flags are forced to 1 by the SAHF command, after which it is checked that the conditional jump instructions JC, JZ, JS, JO are executed. Then, in a similar way, the correct execution of conditional transitions is checked when these flags have zero values. This was later abandoned due to the fact that the incorrect operation of the flags is a very serious processor error, in the presence of which POST will still not reach this test. Also, since 80386, processors have an offline test, and in the presence of such a blunder, it is unlikely that the processor will start POSTing at all.

02 Reserved for ProcessorTest 2. Tests processor registers by writing and test reading. This test was abandoned around step 80386 for the same reason as test 01.
03 It is assumed that the Soyo option is correct, according to which only the EISA resources are configured, and the PIIX resources (DMA, INT, Timer, RTC) are configured in step C0, as described above, however, depending on the specific BIOS version, there may be variations.
NMI (Non Maskable interrupt) is a non-maskable interrupt, has a fixed vector number (2), is used to report emergency situations to the processor (DRAM parity error, IOCCHCK# signal activity on ISA, etc.).
PIE, AIE, UIE (there was a typo in the original Award document, UEI was indicated by mistake) - these are three enable bits for generating an interrupt request by the RealTimeClock circuit (IRQ8 = INT 70h), according to three conditions that can be independently enabled and disabled.
PIE (Periodic Interrupt Enable) - enabling periodic interrupts with a software-set frequency.
AIE (Alarm Interrupt Enable) - enabling interrupts from the alarm clock, generated when the values of hours, minutes, seconds coincide in the time counting registers and alarm clock registers.
UIE (Update Interrupt Enable) - enabling interrupts at the end of the cycle of updating the state of the hour:minute:second counters (1 time per second).
SQWV is a mode for generating a programmable frequency at a special output of the RTC chip. PIE, AIE, UIE, SQWV are disabled when performing POST; for this, the control byte is written accordingly to register 0Bh of the RTC chip.
04 Checking the generation of requests for DRAM regeneration.
In the classic PC AT implementation, requests for DRAM regeneration are generated by channel 1 of the 8254 system timer. A trigger is also connected to its output, operating in counting mode and changing its state to the opposite one with each request. The state of this flip-flop can be read by software via bit 4 of port 61h. The Refresh Toggle test consists of checking that this trigger is toggling at the specified frequency. However, chipsets have emerged that use different DRAM regeneration algorithms in order to minimize CPU downtime due to regeneration. In this case, although the Refresh Trigger is retained for compatibility, it can no longer be used to check the generation of regeneration requests.From this point on it becomes possible to use a stack
05 If you have EGA or VGA adapters installed that are supported by the native BIOS, the Blank Video operation is not possible at this point because the Video BIOS has not yet been initialized. If a CGA or MDA is installed that is supported by the System BIOS video service routines, it is theoretically possible to clear the screen at this step.
Checking and initializing the keyboard controller. A self-test command is sent to the keyboard controller and the status is monitored after completion. Then the command to enable the keyboard interface is sent.
Note 1:At the moment, receiving the codes of pressed keys is not yet possible, since interrupts are disabled, the BIOS data areas are not prepared, and the keyboard itself is not initialized.
06 Test Shadow of the memory area starting at address F000h, where the BIOS is located. Presumably, some actions are performed aimed at additional testing of memory or memory contents, since if the BIOS is placed in Shadow RAM at step C5, it is already too late to test it. Perhaps this step is due to the specification of a particular ChipSet or is present in BIOSes that do not support Early Shadow.
07 Checking the functioning of CMOS and battery power.
Battery power is checked by reading the 0Dh register of the RTC chip. Bit 7 of this register indicates a battery error, and it reports an error even if CMOS power is currently normal, but there has been a loss of CMOS power since register 0Dh was last read. If a power failure is detected, the BIOS remembers this fact, but POST does not stop. Then Verify Basic R/W functionality is performed - checking CMOS cells as a memory check. The values are written, a control reading is performed, and the read code is checked for equality with the written one. Unlike a battery error, an error detected by this test is considered fatal and leads to a stop at code 07.
BE Setting up CHIPSET configuration registers. Programming configuration registers of Host Bridge and PIIX chips. The values are loaded from the BIOS defaults table, accessible to the user using the MODBIN utility.
08 In the current disagreement, Absent is apparently the correct meaning, in view of the fact that the 64K in question here have already been tested, since they are included in the 256K involved in steps C3, C5. OEM Specific steps for the initial configuration of the DRAM Controller have already been completed.
09 IBM/Cyrix processors have internal registers for more flexible caching control. At this step, the CPUID machine instruction is executed to recognize the processor type (apparently, the main CPU recognition procedure occurs much later, at this stage you should find out whether it is IBM/Cyrix or not), if IBM/Cyrix is recognized, its extended cache control registers are initialized.The L2 Cache Controller is being initialized (writing control words to the corresponding registers of the Host Bridge configuration block, clearing TAGRAM).

0A1 Generate interrupt vector table. The table has a volume of 1024 bytes and contains 256 pointers to interrupt handling procedures, for each procedure - two 16-bit words: offset and segment, at this stage 32 vectors are installed (INT 00h - INT 1Fh), to the corresponding interrupt handling procedures (Interrupt Handlers ), included in the BIOS. Vectors 33-120 are installed on the stub procedure. Setting up Power Management resources. This step also involves the initial configuration of the power management subsystem included in the PIIX, the SMI (System Management interrupt) generation circuit, and the installation of the SMI vector.

0B If the INS key is pressed, the default CMOS setting is performed.An essential point for BIOSes that support SoftMenu. (See FAQ #9).
The checksum of the block of CMOS cells responsible for storing configuration information is checked; if an error is detected, the CMOS invalid software flag is set. This flag is also set if a loss of CMOS battery power was detected earlier in step 07.
If the BIOS supports PnP, it scans ISA PnP devices and initializes their parameters (Address, IRQ and DRQ numbers). For PCI devices, the main parameters are set in the configuration register block (PCI Bus Cycle parameters, I/O and MEMORY Address). The PCI device configuration register block contains fields that have the same purpose for all PCI devices (standard) and fields specific to a particular device. Setting the parameters of PCI devices, which is discussed here, comes down to setting the values of standard fields.
P6-class processors have access to firmware memory, which stores the microcode to execute each machine instruction. Making changes to the microcode makes it possible to change the algorithms for executing existing machine commands and add new ones.
0C Initializing the BIOS variable block. At this stage, starting values are assigned to the BIOS variables located in the 256-byte block 0040:0000h - 0040:00FFh.
Disagreements with Initialize Keyboard are apparently being resolved in favor of the Soyo option, since the second blinking of the keyboard LEDs after the power is turned on occurs after the video adapter has been initialized
0D The classic approach to detecting a video adapter is as follows: the presence of EGABIOS or VGABIOS is checked by checking for the presence of the 55 AA signature at the Video BIOS start address (Seg:Offs = C000:0000h). If a signature is detected, the Video BIOS checksum is checked; if it is correct, control is transferred with the CALL FAR command at the address Seg:Offs = C000:0003h to the Video BIOS initialization procedure. This procedure configures the video adapter, resets the interrupt vector INT 10h (Video Service) to the Video BIOS service procedure, displays the video adapter splash screen and returns control to the calling System BIOS procedure with the RET FAR command. If the Video BIOS is not detected, an attempt is made to detect the CGA or MDA by scanning the port space and looking for the CGA/MDA control registers. If CGA or MDA is detected, the BIOS initializes the video adapter. Unlike EGA/VGA, CGA/MDA does not have Video BIOS adapters, and processing INT 10h for CGA/MDA is the responsibility of the System BIOS. If no video adapter is detected, a sound signal is generated.
At the same stage, the type of processor (processors) is recognized, I/O APIC, Local APIC are configured, Host Bridge programming is performed to set Host Bus (Front Side Bus) parameters. To recognize the type of processor, the CPUID command is usually used.
To measure the clock frequency, we use the TSC (Time Stamp Counter) register increment rate, which is incremented for each Internal CPU CLK clock cycle. Either the system timer or the RTC can be used as a reference frequency generator. Some BIOSes do not use a Time Stamp Counter, but rather measure the cycle execution time from a sequence of commands for which the number of clock cycles per command is known. This was done when processors did not have TSC
0E If a CGA or MDA video adapter is installed, the Video RAM test is performed. For EGA/VGA, such a test was performed by Video BIOS at step 0D, when executing the initialization procedure C000:0003h.
Regarding the APIC configuration: it is most likely divided into two stages, performed at steps 0D and 0E.
Presumably this step, rather than 0F, configures the keyboard and enables hardware interrupts from the 8254 timer (IRQ0) and keyboard (IRQ1).
Initializing the RPB (Remote Pre Boot) remote boot subsystem,
0F Checking the first DMA controller 8237, incorrectly specified in the SOYO documentation as channel 0 - the concepts of “DMA channel” and “DMA controller” are confused. The check is performed by writing and test reading the base address and transfer length registers. Actually, test data transfers using DMA channels are not performed at this step and in general during POST. This way, only the read/write of the DMA controller registers by the processor is checked using IN/OUT commands.
BIOS Checksum should have been checked during unpacking, apparently the location of the BIOS Checksum Test at this stage was before the BIOS was divided into Boot Block and the main (packed) block.
It is known that at this stage the keyboard definitions and its internal test are performed. Reset of the keyboard controller and the PS/2 mouse interface it serves are prohibited. These actions are performed later in step 3D.
10 Checking the second DMA 8237 controller.
11 Checking DMA controller page registers. Page registers are needed to expand the 16-bit address generated by the 8237 controller to 24-bit (ISA) or 32-bit (EISA).
The separation of page registers from the DMA controller is due to the fact that in older systems the Intel 8237 DMA controller was used as a separate chip; it is capable of generating only 16-bit addresses, so an additional address expansion unit (DMA Page Registers) was installed.
The test of page registers is performed by writes and control reads, without actual DMA operations (transfers)
14 Test channel (counter) 2 system timer. Channel 2 of the system timer is used to generate sound. According to our information, no classical approach to this test has been formed; some BIOS are limited to writing and control reading of timer registers available for writing and reading (R/W test).
Some BIOSes program a timer to form a specified interval and control the duration of the generated interval using the RTC clock. However, in case of a discrepancy, it is not clear who made the mistake - Timer or RTC. Presumably, Award 4.51 was limited to the R/W test,
15 Checking the request masking register of the first interrupt controller. It should be said that using the term "Channel" for an interrupt controller is unconventional and will lead to confusion. The following designations are accepted: First interrupt controller (Master), 8259#1. Registers are available at 20h, 21h. Processes IRQ0-IRQ7, which are assigned vectors INT 08h - INT 0Fh. Second interrupt controller (Slave), 8259#2. Registers are available at addresses A0h, A1h. Processes IRQ8-IRQ15, which are assigned vectors INT 70h - INT 77h. The output of Slave8259 is connected to the IRQ2 input of Master 8259.
This step checks the masking register of the first interrupt controller by writing test codes to port 21h and test reading. However, IRQ POST does not check the masking operation itself, such as individual permission/denial of IRQ lines.
16 Checking the request masking register of the second interrupt controller. The operation is the same as step 15, the mask register address for the second interrupt controller is A1h.
17 Reserved. Apparently in earlier BIOS versions the following operation was performed at this step: IRQ source devices (Timer, Keyboard...) were programmed in such a way that the IRQ request was fixed in a passive state, then the request registers of interrupt controllers 8259#1 and 8259#2 were read and the fact that the corresponding requests are passive was checked.
The practice of repairing boards shows that fixing the IRQ in state 0 or 1 makes itself felt only at the moment when you need to interact with a device whose IRQ is faulty (this happens in most cases). The interrupt controller test phase does NOT detect such a defect, so it is assumed that the BIOS does not do the specified action.
18 According to the description, this step is similar to step 17, however, if at step 17 the absence of requests was checked, here, on the contrary, IRQ source devices are programmed to activate requests and the launch of interrupt handling procedures for activated requests is checked.
Based on the same experimental data discussed in the description of step 17, we can assume that step 18 is indeed missing in the sense that Award has in mind. There is confirmation of its existence and the execution of completely different test procedures related to determining the type of processor.
19 Checking the passivity of a non-maskable interrupt (NMI) request. The NMI request is used to inform the processor about emergency situations (memory parity error, #IOCHCK signal activity on the ISA bus). It leads to the generation of an interrupt with a fixed vector number - 2 and is processed without the participation of 8259. These emergency events lead to the installation of an NMI trigger, this trigger is reset by software, its status can also be polled (port 61h is used). Typically this test involves performing a soft reset of the NMI trigger and checking that it has not been reset
1A Presumably, this step is Reserved, and the CPU clock frequency is displayed on the screen at step 0D.
1E, 1FSetting EISA bus parameters according to the contents of NV memory (EISA BIOS). The checksum of the EISA parameter block (NVM Checksum) is checked, if it is correct, the EISA controller is initialized in accordance with the specified parameters.
20...2FInitializing EISA devices. Unlike ISA, the EISA bus has facilities for individual slot addressing (separate SELECT signals). Thus, it is possible to programmatically recognize which device is installed in which slot. It is also possible to perform separate access to configuration registers similar to PCI, which is done in this step.
30 1 .Get Base Memory and Extended Memory Size
2.P6 Multi-P BIOS Only - Init I/O and Local APIC

3.Program K5/K6 CPU"s Write Allocation
Determining the volume of Base Memory and Extended Memory. This is the final stage of determining the amount of memory, at this point all mapping operations have been completed, and at this stage memory testing begins, the BIOS performs a write/control read, determines from which address the read values stop matching the written ones and this address is accepted as the memory boundary .
APIC settings in relation to P6 are covered quite little.
K5/K6 Write Allocation is an AMD innovation that boils down to the following. On Intel processors, the reason for caching a cell is only to read it; after a cell with a certain address is cached, this also benefits when writing (Write Back), however, the caching itself is performed only when reading, so if the executing code encounters a series of successive records at the same (or close) addresses, the cache does not benefit if these addresses have not been read by the program before. AMD Write Allocation is a mode in which the reason for caching is not only reading data, but also writing. This is fraught with collisions, like any deviation from the Intel standard, so AMD has provided the ability to programmatically control this mode, even disabling it. Setting up the AMD K5/K6 processor registers that control this mode is part of step 30.

31 1. Test base memory from 256K to 640K and extended memory above 1MB.
2. Test Extended Memory from 1M to the memory using various patterns.
NOTE: This will be skipped in EISA mode and can be "skipped" with ESC key in ISA mode.
3.USB Init.
The main on-screen RAM test. For the amount of memory determined in step 30, a test is performed by writing several types of Pattern and reading them in control. The supposed reason for the disagreement over EISA is the fact that, according to old standards, only an EISA system could have more than 16 MB of memory. Now this is not the case, and all physically present memory is tested at this stage, at least for a non-EISA system.
USB initialization. There are doubts about USB: this action is not related to the memory test and a separate code should have been reserved for it.
32 IfEISA Mode flag is set then test EISA memory found in slots initialization.
NOTE: This will be skipped in ISA mode and can be "skipped" with ESC key in EISA mode.
Display the Award Plug and Play BIOS Extension message (PnP BIOS ONLY).
Program all onboard super I/O chips(if any) including COM ports, LPT ports, FDD port... according to setup value Program onboard audio devices
If we proceed from the assumption that all memory is checked at step 31, then for step 32 the Soyo option seems correct, where there is no mention of memory.
The Plug and Play BIOS Extension splash screen appears.
Setting up Super I/O resources. The SIO chip is entered into configuration mode. In accordance with the Setup settings, if the CMOS is reliable, the following parameters are programmed: base addresses of software-accessible resources COM, LPT, FDC, GamePort, numbers of used IRQ and DRQ lines. After this, the SIO configuration mode is disabled.
The Onboard Audio Device is programmed in the same way. If the Audio Device is connected to PCI, its configuration does not occur in this step, but in step 0B.
39 Programming clock synthesizer by I2C bus.
Presumably, this step involves programming the clock generator via the I2C bus
3C Set flag to allow users to enter CMOS Setup Utility.Setting the software flag to allow entry into Setup.
3D 1. Initialize Keyboard.
2. Install PS2 mouse.
3. Build the INT 15h function E820H table.
4. Build the PnP Device Node for total memory size.
Initializing PS/2 mouse. One of the alternative moments for initializing the keyboard.
There is little information regarding the E820h function and PnP Device Node.
3E Try to turn on Level 2 cache.
NOTE: Some chipset may need to turn on the L2 cache in this stage. But usually, the cache is turn on later in POST 61h.
One of the alternative points for initializing the External Cache controller and Cache resolution
B.F. 1. Program the rest of the Chipset's value according to Setup (Later Setup Value Program).
2. If auto-configuration is enabled, programmed the chipset with pre-defined values in the MODBINable Auto-Table .
Setting up CHIPSET configuration registers in accordance with CHIPSET Setup settings.Available for the MODBIN utility.
40 Display virus protect disable or enable - Absent .
Displaying the status of the Virus Protect option, excluded in new BIOS versions
41 Initialize floppy disk drive controller and any drives.
Initializing the floppy disk subsystem.
For BIOSes that support P6 processors, the local APIC is first disabled because otherwise the IRQ request cannot be generated correctly. Then, for all BIOS types, a soft reset of the drive controller is performed (via port 3F2h). The masking of the interrupt request from the disk drive (IRQ6) is removed; to do this, bit 6 in port 21h is cleared, and the passage of the interrupt request from the disk drive controller is checked. The operating parameters of the drive controller are set (using the SPECIFY command). If Floppy Drive Seek Test is enabled in Setup, a positioning test is performed for installed drives
42 1. Cut IRQ 12 connection if PS2 mouse is not installed.
2. Install IDE Hard Drives. Auto-detect HDDs. Build the AT compatible HDD table for Type 47. Set PIO timing .
3. Detect CD ROM on IDE Bus.
4. Detect LS120 drive.
Disable IRQ12 if PS/2 mouse is missing.
The hard drive controller is being soft reset. If the device is set to AUTO mode in Setup, the IDENTIFY DRIVE command is executed, otherwise the device parameters are taken from CMOS. The PIIX configuration registers are being programmed to set PIO Mode.
A scan is performed for the presence of other IDE devices (CDROM, LS120 ...). If there are devices on the Primary IDE, IRQ14 is unmasked and bit 6 in port A1h is cleared. If there are devices on the Secondary IDE, IRQ15 is unmasked and bit 7 in port A1h is cleared. The passage of the corresponding IRQs is checked (for HDD only)
43 1. Detect and Initialize Serial/Parallel Ports (also game port).
2. If it is a PNP BIOS, initialize serial and parallel ports .
Presumably, the configuration of the Si/o Chip itself occurs at step 32, and at step 43 the SIO resources are added to the list of PnP devices generated by the BIOS.
45 Detect and Initialize math coprocessor.Initializing the FPU coprocessor.
The presence check (Detect) in the usual sense is not performed, since the presence/absence of an FPU clearly follows from the information read by the CPUID command when determining the CPU Type. But since it is impossible to verify the functional suitability of this device in the early stages of POST, a series of tests involving memory are performed to confirm the correctness of the FPU definition.
Initialization usually means software resetting the FPU and writing the control word to the FPU CW register.
4E 1. Reboot if Manufacturing pin POST Loop is set. Otherwise display any messages (i.e., any non-fatal errors that were detected during POST) and enter Setup.
2. If there is any error detected (such as video, keyboard etc.), show all the error messages on the screen and wait for user to press key.
3. Enable "Far Hit" for IBM/Cyrix 6x86 CPU.Initializing the USB keyboard.
Some motherboards (mostly Socket 7) have a jumper for factory testing. If the specified jumper is set, a reboot is performed. Otherwise, messages about non-fatal errors are displayed on the screen, such as the HDD not matching the type declared in CMOS, keyboard failure, and the like.
At this stage, it becomes possible to enter CMOS Setup if you have pressed the DEL key.
If the factory testing jumper is not installed or is not provided at all and errors are detected that do not prevent the further execution of POST and the start of the operating system, a message is displayed and an expectation is to continue POST by pressing any key. For a DIN or PS/2 keyboard, initialization is already done in step 3D, so only the KeyLock status is checked. Other keyboard options are set in step 62.
Due to the fact that at step 45 all initialization procedures for the CPU are completed, it becomes possible to select a protocol for working with cache L2 if an IBM/Cyrix processor is installed. Write Allocation is allowed.
4F 1. If password is needed, ask for password.
2. Clear the Energy Star Logo (Green BIOS ONLY).
Prompts you to enter a password, if provided by the CMOS Setup settings.
The Energy Star Pollution logo or its replacement is disappearing.
50 Write all CMOS values back to RAM and clear screen.
Write all the CMOS values currently in the BIOS stack area back into the CMOS .
Restoring a previously stored CMOS state in RAM. When some POST fragments are executed, the CMOS content may be modified, so the original CMOS content is copied to RAM, usually the BIOS stack, and after passing through the corrupting CMOS fragments, written back to CMOS.
51 Enable parity checker, Enable NMI, Enable cache, reset flags before boot.
There is no information regarding enabling parity, non-maskable interrupts, cache L1/L2 and resetting flags. Presumably, performing these operations is only possible for Intel HX type chipsets that support parity.
Auto-detection of HDD using a 32-bit access scheme is allowed.
Initializing and setting ISA/PnP device parameters before initializing PCI devices
52 1. Initialize any option ROMs present from C8000h to EFFFFh .
NOTE: When FSCAN option is enabled, will initialize from C8000h to F7FFFh .
2. Later PCI initializations (PCI BIOS ONLY) - assign IRQ to PCI devices - initialize all PCI ROMs.
3. Program shadows RAM according to Setup settings.
4. Program parity according to Setup setting.
5. Power Management Initialization. Enable/Disable global PM - APM interface initializtion.
Initialization of additional BIOS ROM (ROMSCAN procedure). The C8000H-EFFFFFH address range is searched for additional BIOS signatures (55 AA), if a signature is found, the block length byte (coming after the signature) is read, the checksum for the block is checked, and if the checksum is correct, control is transferred to the FAR CALL command at offset 0003 relative to the beginning of the block. The secondary BIOS is expected to initialize the device it is servicing, intercept the necessary interrupt vectors, and return control to the System BIOS with the RET FAR command. A typical example is the SCSI BIOS, which usually intercepts INT 13h and takes over the maintenance of the SCSI HDD. Video BIOS uses the same ideology, but is in a special position - its initialization occurs earlier, to ensure that the POST execution can be displayed on the screen.
Assign IRQ to PCI devices - this means setting the values of the four PIIX configuration registers (according to the number of PCI INT lines), which record to which IRQ each of the PCI interrupt request lines is mapped (INTA#, INTB#, INTC#, INTD#) . For additional BIOS, in accordance with the Setup settings, the Shadow mode is optionally enabled. For System BIOS it is always enabled.
At this stage the following is also programmed:
formation of NMI (Nonmaskable Interrupt) for Parity Check
formation of SMI (System Management Interrupt) for Green functions
53 Initialize time value in 40h: BIOS area.
1. If it is NOT a PNP BIOS, initialize serial and parallel ports.
2. Initialize time value in BIOS data area by translate the RTC time value into a timer tick value .
Setting the DOS Time counter in accordance with Real Time Clock. The time value in the hours:minutes:seconds format is converted into 18.2 Hz timer ticks and written to the DOS Time cells in the BIOS variable area. Setting BIOS variables that store base port addresses.
60 SetupVirus Protection (Boot Sector Protection) functionality according to Setupsetting .
Installing BOOT Sector antivirus protection. In most boards, such protection is implemented in software. Before entering the disk service processing procedure (INT 13h), a transit software module is installed that analyzes the input parameters of the function and detects two situations:
Attempt to write to BOOT Sector (AH=3, CL=1, CH=0, DL=8xh, DH=0)
Attempt to format Track 0 (AH=5 , CH=0 , DL=8xh , DH=0 )
If the system of conditions - register values - is met, a warning message and a sound signal are issued instead of a disk operation. At step 60, the vector INT 13h is transferred to the transit control module, if this mode is enabled in Setup.
61 1. Try to turn on Level 2 cache.
Note: if L2 cache is already turned on in POST 3D, this part will be skipped .
2. Set the boot up speed according to Setup setting.
3. Last chance for Chipset initialization.
4. Last chance for Power Management initialization (Green BIOS only) .
5. Show the system configuration table .
One of the alternative points to enable External Cache.
Final steps to initialize Chipset and Power Management
62 1. Setup daylight saving according to Setup value.
2. Program the NUM Lock, typmatic rate and typmatic speed according to Setup setting Reading KBD ID.
Setting the Daylight Saving mode - allowing automatic transition to winter/summer time for RealTimeClock, NUM Lock state, auto-repeat frequency and wait time before entering auto-repeat mode.
63 1. If there is any changes in the hardware configuration, update the ESCD information (PNP BIOS ONLY) .
2. If there is any changes in the hardware configuration, update the DMI data pool (DMI BIOS ONLY) .
3. Clear memory that has been used.
4. Boot system via INT 19h.
Correction of ESCD, DMI blocks if the configuration has changed. Cleaning, resetting RAM.
75 Thermal Warning.
If the LM78 is used as a system monitoring controller, an alarm is issued when the permissible temperature limits are exceeded.
There is currently no reliable information about the generation of this code by controllers from other manufacturers, such as Winbond Electronics or Genesys Logic.
80 ...83 , 90 ...93 Primary Master IDE Power Off(80)/On(90); Primary Slave IDE Power Off(81)/On(91); Secondary Master IDE Power Off(82)/On(92);Secondary Slave IDE Power Off(83)/On(93) .
84 and 94Sound Chip Power Off(84)/On(94) .
86 ...88 , 96 ...98 COMA Power Off(86)/On(96) ; COMB Power Off(87)/On(97) ;LPT Power Off(88)/On(98).
8B and 9BTurn CRT Off(8B)/On(9B) .
85, 89, 8A, 8C, 8D and 95, 99, 9A, 9C, 9DTurn Unknown Devices Off/On .
This is not one of the POST stages, but an output to the diagnostic port of control points for turning on/off unknown devices.
It should be noted that all group 80 and 90 codes are associated with events that occur during the Green Functions process. Today there is no reliable information that unambiguously identifies devices, other than those mentioned above, involved in energy saving functions
B0 Spurious. If interrupt occurs in protected mode.
Stub interrupt (exception) handler for protected mode. This is not one of the POST stages, but a procedure that sets vectors (for protected mode, not vectors, but IDT descriptors) of internal processor interrupts (exceptions) while operating in Protected Mode, for example, during the Extended Memory test. If there are no failures when working in Protected Mode, this procedure will not receive control. If errors occur, such as invalid data in descriptor tables, page violations, and other Protected Mode exceptions, control will be transferred to this procedure, it will output the code B0 on Port 80 and stop
B1 If unmasked NMI occurs, display Press F1 to disable NMI, F2 reboot . Unclaimed NMI occurs.
A stub handler for a non-maskable interrupt. This is not one of the POST steps, but rather a procedure pointed to by the non-maskable interrupt vector. If an NMI request occurs and the cause of the NMI cannot be identified, this code is output to Port80 and the message is displayed:
Press F1 to disable NMI, F2 to reboot.
And user actions are expected.
B2 Unknown action.
55 and BBBegin to Shutdown the system 5 Volt;Begin to Shutdown the system 0 Volt .
D3 SMI Handle.
D7 Software Doze.
D8 Software standby.
D9 Software Suspend.
E1...EF Setup Pages E1 - Page 1, E2 - Page 2, etc.
There is no verified information on this operation; presumably, this is relevant for older systems in which access to the BIOS ROM is organized page by page through a mappable window; when installing each new page, the Ex code is displayed, where x is the page number. This fact is confirmed by the existence in the specified range of codes associated with the execution of other processes
E.C. ECC Post Code associate with System Management Interrupt (SMI) .
There is currently no reliable information about the reasons for generating this code. Presumably, its occurrence is associated with ECC processing during the execution of Green Functions.
ED HDD hang up on 0V resume.
This code indicates an error in exiting the HDD from power saving mode.
FF System Booting.
This means that the BIOS already pass the control right to the operating system.
Transferring control to the BOOT sector loader. The BIOS executes the INT 19h command. The interrupt handling procedure INT 19h sequentially tries to register.

POST cards have been used for decades to diagnose hardware faults in computers and motherboards of various form factors. At the moment, a lot of these cards have been created, for almost all possible situations. The article talks about what POST cards are and what they are used for, how they work, what they are and how they differ from each other.

POST

After pressing the computer's power button, the BIOS carries out a step-by-step check and initialization of all elements of the computer's hardware. This process is called: POST(English: Power-On Self-Test - self-test after switching on). Not only computers, but also most modern electronic devices have similar systems.

BIOS reports status(or the result) of passing POST in several ways:

1. Display messages on the screen. The most friendly and informative way. Essentially, it is only available after successful or nearly successful completion of the self-test. The absence of any information on the screen indicates serious malfunctions of the basic components (motherboard, processor, memory, video adapter, etc.). Error diagnosis is possible mainly only for peripheral devices (drives, keyboard, etc.).

2. Sound signals. Probably everyone has heard a short “beep” when turning on the computer - in most BIOS this means passing the test without errors and being ready to load the OS. Other signal options may indicate certain problems with the hardware. These Morse codes vary between different manufacturers and even different BIOS versions. You can usually find them in the motherboard booklet or relevant online reference books.

3. POST codes. During each step of the self-test process, the BIOS sends the current code to port 80h (sometimes 81h or others), and if an error occurs, either the operation code that failed or the last successful operation code is left there. By reading this code, you can determine at what stage the error occurred and what could have caused it. This is the only one of all the listed methods that allows you to identify problems on a motherboard that does not show visible signs of life. For this reason, it is usually used to diagnose and repair motherboards themselves.

If the first two diagnostic methods do not require special equipment, except perhaps a monitor and a speaker connected to the motherboard (sometimes it is not there), then for the third method you will need the POST card itself.

Where to look for valuesPOST codes and beeps?

Most detailed for all common BIOS versions in Russian and with a transcript they are described on the IC Book website. But there is so much information that it’s easy to get lost, more convenient download ready from there PDF a document with a list of codes (clicking on the desired code in it takes you to a page with a detailed decoding).

I also recommend English-speaking PostCodeMaster resource – it contains even more POST codes and BIOS sound signals from different manufacturers (there are quite rare ones, plus a few for specific motherboards, including server ones).

POST cards

Main task any POST card is to read and display the current POST code. It can be read in several ways: via ISA, PCI, LPC buses or via an LPT port. There are other, more exotic options (more on them later). In addition to actually displaying the code, good POST cards have additional diagnostic capabilities (indicators, testing modes, they are even found with a built-in video adapter).

Some motherboards (usually Premium segment) have built-in POST code indicator.

Previously, many craftsmen made POST cards manually, but now there is absolutely no point in doing this, you will pay more for textolite and components than a regular card costs. If you really want...

ISA

The first POST cards were cards for ISA buses, which existed from 1981 to 1999. It is used even now (albeit very rarely), mainly in the industrial and military sectors - where the equipment for this bus remains. POST cards for it are also sold, both in a separate version (ISA only) and ISA + PCI combines.

If you are not doing 486 repairs, then having a POST ISA card is not at all necessary.

PCI

The next popular computer bus was PCI. It is now the most common bus for desktop computers. Naturally, there are also POST cards for it of all possible shapes, sizes and functions. Most the simplest, with a regular segment indicator, can be bought for 2-3 bucks on any Ebay, Ali and the like.

In principle, such a card copes with its basic task quite well - you will recognize the POST code. But this is not enough for professional work. Useful to have indicators main voltages (usually: +5, +3.3, +12, -12, +3.3 Standby) and bus signal indicators (from the most basic: CLK, RST#, FRAME#, IRDY#). It is important to be able to switch the port on which the card “listens” for POST codes (not just the standard 80h). There are other “tricks”, hence the “sophisticated” appearance of advanced cards.

Typically, POST cards are installed on obviously faulty motherboards (in fact, this is what they are intended for), and cases cannot be excluded failure the POST card itself during testing. Therefore, it’s a good idea to have a simple, cheap card for initial diagnostics.

Another convenient option- This is a remote indicator. It allows you to easily diagnose motherboards without removing them from the system unit. On the one hand, if it comes to the POST card, then most likely the motherboard will still have to be removed for repair, but on the other hand, this is not always the case, and the POST card is just a convenient way of general diagnostics. The photo shows Sintech ST8679, a Chinese card with a remote multi-line LCD display.

LPT

There are POST cards for LPT port - quite simple and a convenient diagnostic method for any computer or laptop that has this same LPT port. Due to technical features, they Dont Have capabilities inherent in cards for PCI, but this is compensated by simplicity and accessibility. Requires power via USB (for this purpose there is a port on the board).

However, LPT is becoming obsolete, and you can hardly see them on modern computers anymore, so these cards are also seeing their days.

PCI-E

PCI, which served us faithfully for many years, gradually displaces more modern PCI-Express. A considerable number of modern motherboards do not have a PCI slot at all (although they may have the bus itself). I can you please– POST cards for PCI-E exist. For example, the American company Ultra-X offers one (their prices are usually wild, but there are no prices or even information here), on the Internet you can find photos of engineering PCI-E cards from Gigabyte (apparently, only for internal use).

Eat and Chinese version PCI-EPOST cards entitled KQCPET6-H. It is produced by a Chinese company QiGuan Electronics, specializing in the production of various kinds of diagnostic cards (and quite interesting ones). Their official website (www.qiguaninc.com), unfortunately, has not been updated for a long time, and there is no information about this card there, but you can easily buy for 20 +/- bucks on Ali.

But with PCI-E it's not that simple. Firstly, diagnostics using PCI-E itself is currently a murky thing, if only due to the lack of adequate information. Secondly, with PCI-E everything depends on the specific manufacturer - there is no guarantee that the codes will be output; if they are output, there is no guarantee that it will be via a standard port and in a standard form...

How can you get POST codes from a board without PCI if you don’t have a PCI-E card at hand? It is impossible to give a definite answer to this question. If your motherboard has built-in indicator- consider yourself very lucky. Can be used LPT, if there is one, of course. Well, the last option is to use a tire LPC, some motherboards have ready-made connectors (LPC_DEBUG, etc.). Even if they are not there, the bus itself is always present, but you will have to “solder on”...

USB

One of the most promising Diagnostic methods today are USB. And the main reason for this is the ubiquitous prevalence this interface. As we have already found out, the absence of one or another connector on the motherboard can become a stumbling block for diagnostics. And USB solves this problem – literally all computers and laptops released over the last 15 years have a couple of ports.

For such a diagnosis it is necessary Availability in USB system DebugPort is a kind of USB extension that allows you to transfer diagnostic information. In USB 3.0, the implementation of Debug Port turned out to be more convenient (you can read more about Debug Port at the link). In addition to transmitting POST codes, Debug Port allows you to full-fledged debugging BIOS and UEFI code.

There was even released different companies. NET20DC from Ajays(the company almost immediately went bankrupt, as suppliers refused to supply them with components to assemble the device). Insyde H 2 O DDT from Insider Software(released, it seems, in 2008, but information about this device has sunk into oblivion even on the official website). Both of these devices are more like debuggers, although they have the ability to capture POST codes.

Most advanced And full-fledged diagnostic tool is AMIDebug Rx from AMI: allows you to display POST codes with a description, fully works with UEFI, keeps a log of the POST process, can be connected to a PC to configure and read codes, has debugger functions. The most interesting thing is that this miracle has yet to be released in 2009 year! It is clear that the device is intended for native AMIBIOS Whether it works with other BIOSes is unknown to me.

In 6-7 years since the appearance of these USB devices, none of them has not gained popularity, now you can only buy AMIDebug Rx, and then only directly from the manufacturer on an individual basis request. The price of the device is not disclosed. So, a widespread transition to USB diagnostics is not yet expected.

Laptop diagnostics

With laptops everything is a little more complicated. The most common connectors that can be used for diagnostics are mini PCI or Mini PCI-E(for more modern ones).

Mini PCI-E (like PCI-E) is not required to output POST codes; it all depends on whether the manufacturer has provided this capability or not.

Again, there is a use case tiresLPC. On motherboards there may well not be a port for connecting to this bus, so you will have to solder directly to the board or controller.

Some manufacturers have your ways diagnostics, here it really is “who knows what”. Unfortunately, this information is usually the property of only the manufacturer and its internal service centers, so all existing options for POST cards are unlikely to be publicly available. Most comprehensive an “all in one bottle” combine for diagnosing laptops is the Sintech ST8675 POST card, which is easy to find from Chinese sellers for $20-30 with delivery.

Among the interesting solutions, the Russian company BVG-Group offers a VGA dongle for Samsung laptops, and cards in the form of a memory module for ASUS laptops. These are probably the most “exotic” POST card options that I know. Although applause should rather be given to laptop manufacturers who came up with just such a diagnostic method for their products.

I may disappoint those who were waiting for specific examples - the POST card is one from diagnostic tools, which in most cases only helps to understand “where to dig”, and how to dig and with what shovel depends entirely on you. Sometimes, to make a “diagnosis,” only one may be enough, or you may need the help of a multimeter and an oscilloscope, complete with the ability to use them. If this causes you difficulties, then it is better to take your motherboard to specialists before it goes from non-working to beyond repair.

PS

POST cards have such an interesting past and rich present. What does the future hold for them? Wait and see. But the reality is that in the current era of consumerism, devices are often disposed of before they have time to break down. And if they break down, they end up in the manufacturer’s service workshops, where they obviously should have suitable diagnostic equipment. All this, in my opinion, is the main reason for the resulting “POST vacuum”.

Compaq BIOS:

	Error Message	Description
		System is booting properly
	BIOS ROM checksum error	The contents of the BIOS ROM to not match the expected contents. If possible, reload the BIOS from the PAQ

		Check the video adapter and ensure it"s seated properly. If possible, replace the video adapter
7 beeps (1 long, 1s, 1l, 1 short, pause, 1 long, 1 short, 1 short)		The AGP video card is faulty. Reseat the card or replace it outright. This beep pertains to Compaq Deskpro systems
1 long never ending beep		Memory error. Bad RAM. Replace and test
		Reseat RAM then retest; replace RAM if failure continues

IBM Desktop BIOS:

	Error Message	Description
		System is booting properly
	Initialization error	Error code is displayed
	System board error
	Video adapter error
	EGA/VGA adapter error
	3270 keyboard adapter error
	Power supply error	Replace the power supply
	Power supply error	Replace the power supply
		Replace the power supply

IBM Thinkpad BIOS:

Beeps/Error	Description
Continuous beeping	System board failure
One beep; Unreadable, blank or flashing LCD	LCD connector problem; LCD backlight inverter failure; video adapter faulty; LCD assembly faulty; System board failure; power supply failure
One beep; Message "Unable to access boot source"	Boot device failure; system board failure
One long, two short beeps	System board failure; Video adapter problem; LCD assembly failure
One long, four short beeps	Low battery voltage
One beep every second	Low battery voltage
Two short beeps with error codes	POST error message
	System board failure

IBM Intellistation BIOS:

Beep error code:	Action / Run diagnostics on the following components:
1-1-3 CMOS read/write error	1.Run Setup 2.System Board
1-1-4 ROM BIOS check error	1.System Board
1-2-X DMA error	1.System Board
1-3-X	1.Memory Module 2.System Board
1-4-4	1. Keyboard 2.System Board
1-4-X Error detected in first 64 KB of RAM.	1.Memory Module 2.System Board
2-1-1, 2-1-2	1.Run Setup 2.System Board
2-1-X First 64 KB of RAM failed.	1.Memory Module 2.System Board
2-2-2	2.System Board
2-2-X First 64 KB of RAM failed.	1.Memory Module 2.System Board
2-3-X	1.Memory Module 2.System Board
2-4-X	1.Run Setup 2. Memory Module 3.System Board
3-1-X DMA register failed.	1.System Board
3-2-4 Keyboard controller failed.	1.System Board 2. Keyboard
3-3-4 Screen initialization failed.	1. Video Adapter (if installed) 2.System Board 3.Display
3-4-1 Screen retrace detected an error.	1. Video Adapter (if installed) 2.System Board 3.Display
3-4-2 POST is searching for video ROM.	1. Video Adapter (if installed) 2.System Board
4	1. Video Adapter (if installed) 2.System Board
All other beep code sequences.	1.System Board
One long and one short beep during POST. Base 640 KB memory error or shadow RAM error.	1.Memory Module 2.System Board
One long beep and two or three short beeps during POST.(Video error)	1. Video Adapter (if installed) 2.System Board
Three short beeps during POST.	1. See "System board memory" on page 62. 2.System Board
Continuous beep.	1.System Board
Repeating short beeps.	1. Keyboard stuck key? 2.Keyboard Cable 3.System Board

Mylex BIOS:

	Error Message	Description
		System is booting normally
	Video adapter error	The video adapter is either faulty or not seated properly. Check the adapter
	Keyboard controller error	The keyboard controller IC is faulty. Replace the IC if possible
		The keyboard controller IC is faulty or the keyboard is faulty. Replace the keyboard, if problem still persists, replace the keyboard controller IC
		The programmable interrupt controller is faulty. Replace the IC if possible
		The programmable interrupt controller is faulty. replace the IC if possible
	DMA page register error	The DMA controller IC is faulty. Replace the IC if possible
	RAM refresh error

	RAM parity error
	DMA controller 0 error	The DMA controller IC for channel 0 has failed
		The CMOS RAM has failed
	DMA controller 1 error	The DMA controller IC for channel 1 has failed
	CMOS RAM battery error	The CMOS RAM battery has failed. If possible, replace the CMOS or battery
	CMOS RAM checksum error	The CMOS RAM has failed. If possible, replace the CMOS
	BIOS ROM checksum error	The BIOS ROM has failed. If possible replace the BIOS or upgrade it

Mylex 386 BIOS:

	Error Message	Description
		System is booting normally
	Video adapter failure	Either the video adapter is faulty, not seated properly or is missing
1 long, 1 short, 1 long	Keyboard controller error	Either the keyboard controller IC is faulty or the system board circuitry is faulty
1 long, 2 short, 1 long		Either the keyboard controller is faulty or the system board circuitry is faulty
1 long, 3 short, 1 long
1 long 4 short, 1 long		The programmable interrupt controller IC is faulty
1 long, 5 short, 1 long	DMA page register error	The DMA controller IC 1 or 2 is faulty or the system board circuitry is faulty
1 long, 6 short, 1 long	RAM refresh error
1 long, 7 short, 1 long
1 long, 8 short, 1 long	RAM parity error
1 long, 9 short, 1 long	DMA controller 1 error	The DMA controller for channel 0 is faulty or the system board circuitry is faulty
1 long, 10 short, 1 long		Either the CMOS RAM is faulty. Replace the CMOS
1 long, 11 short, 1 long	DMA controller 2 error	The DMA controller for channel 1 is faulty or the system board circuitry is faulty
1 long, 12 short, 1 long	CMOS RAM battery error	The CMOS RAM battery is faulty or the CMOS RAM is bad. Replace the battery if possible
1 long, 13 short, 1 long	CMOS checksum error	The CMOS RAM is faulty
1 long 14 short, 1 long	BIOS ROM checksum failure	The BIOS ROM checksum is faulty. Replace the BIOS or upgrade

Phoenix ISA/MCA/EISA BIOS:

The beep codes are represented in the number of beeps. E.g. 1-1-2 would mean 1 beep, a pause, 1 beep, a pause, and 2 beeps.

With a Dell computer, a 1-2 beep code can also indicate that a bootable add-in card is installed but no boot device is attached. For example, in you insert a Promise Ultra-66 card but do not connect a hard drive to it, you will get the beep code. I verified this with a SIIG (crap -- avoid like the plague) Ultra-66 card, and then confirmed the results with Dell.

	Error Message	Description
	CPU test failure	The CPU is faulty. Replace the CPU
	System board select failure	The motherboard is having an undetermined fault. Replace the motherboard
	CMOS read/write error	The real time clock/CMOS is faulty. Replace the CMOS if possible
	Extended CMOS RAM failure	The extended portion of the CMOS RAM has failed. Replace the CMOS if possible
	BIOS ROM checksum error	The BIOS ROM has failed. Replace the BIOS or upgrade if possible
		The programmable interrupt timer has failed. Replace if possible

	DMA read/write failure	The DMA controller has failed. Replace the IC if possible
	RAM refresh failure	The RAM refresh controller has failed
	64KB RAM failure	The test of the first 64KB RAM has failed to start
	First 64KB RAM failure	The first RAM IC has failed. Replace the IC if possible
	First 64KB logic failure	The first RAM control logic has failed
	Address line failure	The address line to the first 64KB RAM has failed
	Parity RAM failure	The first RAM IC has failed. Replace if possible
	EISA fail-safe timer test	Replace the motherboard
	EISA NMI port 462 test	Replace the motherboard
	64KB RAM failure	Bit 0; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 1; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 2; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 3; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 4; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 5; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 6; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 7; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 8; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 9; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 10; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 11; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 12; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 13; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 14; This data bit on the first RAM IC has failed. Replace the IC if possible
	64KB RAM failure	Bit 15; This data bit on the first RAM IC has failed. Replace the IC if possible
	Slave DMA register failure	The DMA controller has failed. Replace the controller if possible
	Master DMA register failure	The DMA controller had failed. Replace the controller if possible
	Master interrupt mask register failure
	Slave interrupt mask register failure	The interrupt controller IC has failed
	Interrupt vector error	The BIOS was unable to load the interrupt vectors into memory. Replace the motherboard

	Keyboard controller failure
	CMOS RAM power bad	Replace the CMOS battery or CMOS RAM if possible
	CMOS configuration error	The CMOS configuration has failed. Restore the configuration or replace the battery if possible

	Video memory failure	There is a problem with the video memory. Replace the video adapter if possible
	Video initialization failure	There is a problem with the video adapter. Reseat the adapter or replace the adapter if possible
		The system's timer IC has failed. Replace the IC if possible
	Shutdown failure	The CMOS has failed. Replace the CMOS IC if possible
	Gate A20 failure	The keyboard controller has failed. Replace the IC if possible
	Unexpected interrupt in protected mode	This is a CPU problem. Replace the CPU and retest
	RAM test failure	System RAM addressing circuitry is faulty. Replace the motherboard
	Interval timer channel 2 failure	The system timer IC has failed. Replace the IC if possible
	Time of day clock failure	The real time clock/CMOS has failed. Replace the CMOS if possible
	Serial port failure	A error has occurred in the serial port circuitry
	Parallel port failure	A error has occurred in the parallel port circuitry
	Math coprocessor failure	The math coprocessor has failed. If possible, replace the MPU

	Description
	Verify real mode

	Initialize system hardware
	Initialize chipset registers with initial values
	Set in POST flag
	Initialize CPU registers
	Initialize cache to initial values

	Initialize power management
	Load alternative registers with initial POST values
	Jump to UserPatch0
	Initialize timer initialization
	8254 timer initialization
	8237 DMA controller initialization
	Reset Programmable Interrupt Controller
	Test DRAM refresh
	Test 8742 Keyboard Controller
	Set ES segment register to 4GB

	Clear 512K base memory
	Test 512K base address lines
	Test 51K base memory
	Test CPU bus-clock frequency
	CMOS RAM read/write failure (this commonly indicates a problem on the ISA bus such as a card not seated)
	Reinitialize the chipset
	Shadow system BIOS ROM
	Reinitialize the cache
	Autosize the cache
	Configure advanced chipset registers
	Load alternate registers with CMOS values
	Set initial CPU speed
	Initialize interrupt vectors
	Initialize BIOS interrupts
	Check ROM copyright notice
	Initialize manager for PCI Options ROMs
	Check video configuration against CMOS
	Initialize PCI bus and devices
	initialize all video adapters in system
	Shadow video BIOS ROM
	Display copyright notice
	Display CPU type and speed

	Set key click if enabled

	Test for unexpected interrupts
	Display prompt "Press F2 to enter setup"
	Test RAM between 512K and 640K
	Test expanded memory
	Test extended memory address lines
	Jump to UserPatch1

	Configure advanced cache registers
	Enable external and CPU caches
	Initialize SMI handler
	Display external cache size
	Display shadow message
	Display non-disposable segments
	Display error messages
	Check for configuration errors
	Test real-time clock
	Check for keyboard errors
	Setup hardware interrupt vectors
	Test coprocessor if present
	Disable onboard I/O ports
	Detect and install external RS232 ports
	Detect and install external parallel ports
	Reinitialize onboard I/O ports
	Initialize BIOS Data Area
	Initialize Extended BIOS Data Area
	Initialize floppy controller
	Initialize hard disk controller
	Initialize local bus hard disk controller
	Jump to UserPatch2
	Disable A20 address line
	Clear huge ES segment register
	Search for option ROMs
	Shadow option ROMs
	Setup power management
	Enable hardware interrupts



	Scan for F2 keystroke

	Clear in-POST flag
	Check for errors
	POST done - prepare to boot operating system

	Check password (optional)
	Clear global descriptor table
	Clear parity checkers
	Check virus and backup reminders
	Try to boot with INT 19
	Interrupt handler error
	Unknown interrupt error
	Pending interrupt error
	Initialize option ROM error

	Extended Block Move
	Shutdown 10 error
	Keyboard Controller failure (most likely problem is with RAM or cache unless no video is present)
	Initialize the chipset
	Initialize refresh counter
	Check for Forced Flash

	Do a complete RAM test
	Do OEM initialization
	Initialize interrupt controller
	Read in bootstrap code
	Initialize all vectors
	Initialize the boot device
	Boot code was read OK

Quadtel BIOS:

	Error Messages	Description
		System is booting normally
		The CMOS RAM is faulty. Replace the IC if possible
		The video adapter is faulty. Reseat the video adapter or replace the adapter if possible
	Peripheral controller error	One or more of the system peripheral controllers is bad. Replace the controllers and retest