Interrupts and special cases. Interrupt Examples

In PC architecture basic system input/output (I/O) occupies a special place. It can be considered, on the one hand, as an integral part of the hardware, on the other hand, this system is one of software modules OS.

One of important function BSVV - service system calls, or interrupts. System calls are generated by software or hardware to perform various operations. The interrupt mechanism is used to implement system calls. The essence of this mechanism is that the current operation of the machine, whatever it may be, can be suspended for a short time one of the signals that indicates the occurrence of a situation requiring immediate processing

Interrupt - this is stopping the execution of the current command or the current sequence of commands to handle some event special program - interrupt handler, followed by a return to the execution of the interrupted program.

The event can be caused by a special situation that arises during program execution, or by a signal from an external device. The interrupt is used to quickly react to special situations that arise during program execution and interaction with the processor. external devices.

When interrupted, the OS saves processor state – register values ​​and meaning program counter (PC)– addresses of the interrupted command . The interrupt handler in the OS determines from the contents of the object code segment what type of interruption has occurred and what actions should be taken to handle it. Among possible types interrupts other than commit various errors, there are also timer interrupts– periodic interruptions after a certain time slice, intended for device polling– actions operating system by periodically checking the status of all ports and external devices, which may change over time: for example, a flash drive was connected to the USB port; the printer finished printing and became free, etc. The OS performs system reconfiguration and adjusts system tables that store information about the device

The interrupt mechanism is provided by appropriate computer hardware and software.

Any exception that causes an interrupt is accompanied by a signal called an interrupt request (IR). Interrupt requests from external devices arrive at the processor via special lines, and requests that arise during program execution come directly from inside the microprocessor. The mechanisms for handling interrupts of both types are similar. Let's consider the functioning of a computer when an interrupt request signal appears, relying mainly on the processing of hardware interrupts (Fig. 13).

Rice. 13. Performing an interrupt in a computer:

tр - processor response time to an interrupt request;

tс - time of saving the state of the interrupted program and calling the interrupt handler;

tв is the recovery time of the interrupted program.

After the interrupt request signal appears, the computer proceeds to execute the program - the interrupt handler. The handler performs those actions that are necessary in connection with the exceptional situation that has arisen. For example, such a situation could be pressing a key on a computer keyboard. Then the handler must pass the code of the pressed key from the keyboard controller to the processor and possibly parse this code. When the handler completes its work, control is transferred to the interrupted program.

Reaction time- this is the time between the appearance of the interrupt request signal and the start of execution of the interrupting program (interrupt handler) if this interrupt is enabled for service.

The response time depends on the moment when the processor determines that an interrupt request has occurred. Polling of interrupt requests can be carried out either after the completion of the next stage of the command (for example, reading a command, reading the first operand, etc.), or after completing each command in the program.

Interrupts can be divided into three groups: hardware, logical and software.

Sources hardware interrupts – drop in supply voltage, pressing a key on the keyboard, arrival of the next pulse from the time counter, occurrence of special signals from storage devices on flexible or hard drives and etc.

Logical, or processor, interrupts occur under different non-standard situations in the operation of the main microprocessor - division by zero, register overflow, the appearance of a “breakpoint”, etc.

Software interrupts– the most extensive category. They are produced when one program wants to receive a certain service from another program, and this service is usually associated with the operation of hardware.

Each interrupt has a unique number and can be associated with a specific subroutine designed to service the situation that has arisen. The service subroutine itself, generally speaking, can also be suspended by another interrupt; but more often than not, during the period of operation of a subroutine servicing a certain interrupt, other interrupts are “masked,” that is, they are not serviced immediately, but are queued.

In the hardware components of the machine in the DOS itself and in application programs interrupts may be generated that need to be serviced. BSVV is entrusted with the task of servicing interrupts lower level– those that require direct control of hardware components. These interrupts are numbered 0 to 31 (hex numbers 0 - 1F). Other interrupts - numbers 32 - 63 (hex numbers 20 - 3F) - belong to a higher level, and their maintenance is assigned to other OS modules.

In table 3 shows a general list of interrupts serviced by the BSVV. IN real programs In assembly language and in OS technical literature, interrupts are identified by hexadecimal codes. From the analysis of table. 3 it is clear that the interrupts serviced by BSVV correspond to basic operations for controlling external devices - display, keyboard, float drive, printer, communication channels. In this case, the subroutines included in the BSVM perform lower-level operations. For example, servicing a floppy disk drive includes the ability to initially install magnetic heads, check the current status of the device, directly read and write specified disk sectors, verify read or written data, and, finally, format (initial layout) disks.

Table 3. Interrupts served by BSVV

Decimal number	Hexadecimal number
		Division by zero
		Converting microprocessor to step by step mode
		Supply voltage drop
		Appearing a breakpoint in a command sequence
		Arithmetic unit register overflow
		Printing a graphic copy of the screen
		Reserved
		Reserved
		Signal from time counter - timer
		Signal from pressing a key on the keyboard
	A	Reserved
Decimal number	Hexadecimal number	Situation served or function performed
	IN	Reserved
	WITH	Reserved
	D	Reserved
	E	Signal about the end of exchange with NMD
	F	Reserved for printer maintenance
		Display control
		Request a list of connected equipment
		Request size physical memory
		NMD management
		Communication adapter management
		Controlling a tape recorder and other devices
		Keyboard control
		Printer management
		Accessing the BASIC built into the ROM
		Restarting the system
	1A	Query/set current time and date
	1B
	1C
	1D	Address of the display initialization parameter table.
	1E	Address of the NGMD parameters table
	1F	Address of the symbol table with codes 128-255

Some of those listed in table. 3 interrupts provide access to several interrelated functions. Each function is identified by its hexadecimal number (code) and performs some particular operation.

So, for example, interrupt 19 (control of the NGMD and NMD) provides access to 18 functions with codes 0-17):

0 - initial installation (disk reset),

1 - displaying the current disk status,

2 - reading a group (block) of sectors from one track,

3 - recording a group of sectors onto one track,

4 - verification after reading or writing,

5 - track formatting (recording sector marks),

8 - issuance of current drive parameters,

9 - initialization of the parameter table fixed disk,

A - “long” reading,

B - “long” record,

C - search for the desired track,

D - initial disk installation,

10 - checking disk readiness,

11 - disk calibration,

14 - controller diagnostics,

15 - issue drive type,

16 - change disk status,

17 - setting the drive type.

Interrupt depth- the maximum number of programs that can interrupt each other. The interrupt depth usually matches the number of priority levels recognized by the interrupt system. The operation of the interrupt system at different interrupt depths (n) is shown in Fig. 10. It is assumed here that as the interrupt request number increases, its priority increases.

Rice. 14. Operation of the interrupt system at different interrupt depths

When an interrupt request is received, the computer executes the following sequence actions:

1) determination of the highest priority unmasked interrupt request (if several requests were received simultaneously);

2) determining the type of selected request;

3)saving the current state of the program counter and flag register;

4) determining the address of the interrupt handler by interrupt type and transferring control to the first command of this handler;

5) execution of the program - interrupt handler;

6)restoring the saved values ​​of the program counter and flag register of the interrupted program;

7) continuation of execution of the interrupted program.

Stages 1-4 are performed automatically by the computer hardware when an interrupt request appears. Stage 6 is also executed in hardware on a return command from the interrupt handler.

The transition to the corresponding interrupt handler is carried out (in real mode microprocessor operation) through the interrupt vector table. This table is located in the lowest addresses random access memory, has a volume of 1 KB and contains the values ​​of the command segment register (CS) and instruction pointer (IP) for 256 interrupt handlers.

Interrupt vector– a memory cell containing the address of the interrupt handler.

Interrupt vectors are combined into an interrupt vector table. The location of the table depends on the type and operating mode of the microprocessor.

The main functions of the interrupt mechanism:

1.Recognition or classification of interruption.

2. Transfer of control to the interrupt handler.

3. Correct return to the interrupted program

The transition from the interrupted program to the handler and back should be done as quickly as possible. One of quick methods is to use a table containing a list of all interrupts allowed for the computer and the addresses of the corresponding handlers. To correctly return to an interrupted program, before transferring control to the handler, the contents of the processor registers are stored either in direct access memory or on the system stack.

Since interrupt signals occur at random times, at the time of the interrupt there may be several interrupt signals that can only be processed sequentially. To process interrupt signals in a reasonable order, they are assigned priorities. Programs, by managing special mask registers, allow you to implement various service disciplines:

Nested interrupts.

For nested interrupts, the processing procedure current interrupt can be interrupted (delayed) upon receipt of an interrupt request that has a higher priority level. After processing an interrupt with more high level priority, the processor returns to the interrupted procedure and continues processing this interrupt until it ends or until a new interrupt occurs. Obviously, an interrupt service routine with a higher priority level can in turn be interrupted by an interrupt with an even higher priority level, and so on. At the same time, interrupts that have more low level priority compared to the current one are usually prohibited (masked).

3. Examples of interrupts

3.1. Interrupt when signal changes on I/O ports (example in PROTEUS)

3.2. External interrupt INT (example in PROTEUS)

All types of dsPIC microcontrollers have the same interrupts. Therefore, you can safely study interrupts in the PROTEUS program. For the study we will use a microcontroller, which is available in PROTEUS.

So, what kind of interrupts exist in the dsPIC33FJ32GP204 microcontroller?

And there are a lot of interruptions in the microcontroller. And it makes no sense to list everything in this lecture. After all, the first thing we pay attention to when choosing a microcontroller is what modules it has, and only then we look at what interruptions it has. We will also study everything in the same sequence. As we study the microcontroller, we will analyze the interrupts of various modules.

In general, you need to know that for the microcontroller there is a table of interrupt vectors, which is located in the program memory. Each interrupt has its own vector, i.e. the address of the start of the specific interrupt routine (ISR). There is also an alternative interrupt vector table. Using a single ALTINV bit, you can specify from which table the address of the interrupt routine should be taken. That is, there is an alternative to the main table. But you need to remember that the ALTINV bit is used for the entire table at once. And if an alternative table is installed, then absolutely all addresses of the interrupt handling subroutine, the main program will be taken from the alternative table. The alternative table is very useful for debugging mode, as it allows you to write a program to the controller once and, using, for example, a button, choose between two program algorithms.

dsPIC has expanded the range of interrupt priorities. If in PIC18 there were only 2 of them, then in dsPIC there are already 8 levels. And when I was developing a module for communication via GPRS channel, this was very useful to me, since the microcontroller used almost all the peripherals available on board, and the number of interrupts processed was about twenty.

The most important thing you need to know is that to work with each interrupt, there are only 3 main bits (registers): the interrupt enable bit, the interrupt flag, and three interrupt priority selection bits.

So, what does a programmer need from a programmer to work with an interrupt:

1. It needs to enable a specific interrupt.

2. After the event that caused the interrupt has occurred, the corresponding interrupt flag is set, and the program, so to speak, moves along the interrupt vector. And if we say in normal language: then as soon as an interruption occurs, the subroutine for processing a specific interrupt will be immediately called.

3. The main thing is not to forget to reset the flag of this very interruption in the interrupt subroutine.

For the dsPIC microcontroller, the C30 compiler provides the following rule for describing interrupt handling routines, for example for the INT1 interrupt:

void __ attribute__((__ interrupt__)) _ INT1 Interrupt()

The main thing you need to pay attention to is the end of the subroutine title text: _ INT1 Interrupt() - this is the only parameter that must be changed for various types interrupts. Each interrupt from the interrupt vector table has its own designation this parameter. And here you will have to open the help file for the C30 compiler, in particular the section (I have this...) “dsPIC30F DSCs (SMPS) Interrupt Vectors” and look at the table of which interrupt should be called in what way. I don’t think it’s advisable to present this table in this article, since anyone who has a C30 compiler should have a help file attached hlpMPLABC30.chm(personally, that’s what I call it). And for those who don’t have this compiler, they don’t need a table J. Okay, let’s digress...

By the way, if you get more deeply acquainted with the principles of describing the interrupt function, you will find the presence of a special attribute auto_psv. This parameter is intended to instruct the microcontroller that it should save the main registers before proceeding to interrupt processing. I assume that you know why you need to save key registers.

For example, the interrupt description would look like this:

void__attribute__((interrupt, auto_psv)) _INT1Interrupt()

Above was an example of a subroutine call header using the address of the main table. And for an alternative table you only need to insert in the variable parameter after the underscore Alt, For example:

_ INT1 Interrupt() -> _ AltINT1 Interrupt()

I would like to draw your attention to the fact that although the interrupt subroutine looks like a subroutine, it does not need to be declared, just like main , since it is already declared by the compiler, you only need to correctly write the header of the interrupt handling subroutine.

Let's start by studying elementary interrupts, and then as we study each module, we will become familiar with the interrupts inherent in them.

3.1. Interrupt when signal changes on I/O ports (CN)

One of the easiest interrupts to understand is the state change interrupt at the CN input. The dsPIC33FJ32GP204 microcontroller is full of such inputs, so I think this number will satisfy any needs. No matter which state changes on these channels (1 -> 0 or 0 -> 1), this change, if enabled, will cause the CNIF flag to be set. In order to activate an interrupt when a signal changes, you need to do the following:

1. Configure necessary channels CN to input (using the TRISx register).

2. Enable control of signal changes at the corresponding CN input. For this there are already 2 registers CNEN1 and CNEN2. You can either access each register entirely for setting, or access the corresponding bits (for example, _CN15IE=1; _CN6IE=1;)

3. If necessary, turn on the pull-up resistors. For this purpose there are also two registers CNPU1 and CNPU2. It is also possible separately, for example _CN15PUE=1; _CN6PUE=1;

4. Enable interrupt when the signal changes on CN ( _ CNIE=1 )

5. Now, as soon as the signal on the controlled CN pins changes, the _CNIF interrupt flag will be set. And the program enters the interrupt handling function. The C30 compiler for interrupting when a signal changes on CN provides the following description of the function:

void __ attribute __((__ interrupt __)) _ CNInterrupt ()

This is where this interrupt is processed (see example)

6. In the interrupt handling subroutine, do not forget to reset the interrupt flag.

To familiarize yourself with this type of interrupt, consider the following example. There is a motor and 4 sensors. When everything is in order, the engine should rotate counterclockwise. But as soon as the sensor state changes ( emergency mode) – the engine should immediately begin to rotate in reverse side(clockwise). And after a given period of time, begin to rotate counterclockwise again.

A metal detector is implemented similarly on harvesting machines. When, for example, mown grass enters the machine, it normal mode work. But as soon as the metal detector detects a metal object, it instantly reverses and the machine seems to spit out this metal object so as not to damage the mechanism. And metal is detected by a special sensor, consisting of several independent channels, but combined into one general device. In our example, we will, of course, simplify everything very much; instead of a metal presence sensor, we will use ordinary buttons.

Assembling the circuit in PROTEUS

Now let’s create a program to complete the task.

# include " p33 Fxxxx. h"

_ FOSCSEL(0 x02);

_ FOSC(0 xE2);

char state; // variable stores the direction of rotation of the motor

// "1" - emergency mode, "0" - normal mode

void init (void);

void init (void)

{ _ CN8 PUE=1; //turn on the pull-up resistor at input CN8 (RC0)

_ CN10 PUE=1; //turn on the pull-up resistor at input CN10 (RC2)

_ CN17 PUE=1; //turn on the pull-up resistor at input CN17 (RC7)

_ CN19 PUE=1; //turn on the pull-up resistor at input CN19 (RC9)

AD1 PCFGL=0 xffff;

PORTC=0; // initialize port C

LATC=0;

TRISC=0 xFFFF; // set up port C as input

PORTC=0 xFFFF;

PORTA=0; // initialize port A

LATA=0;

TRISA=0; // Set all output to output,

PORTA=0;

_ CN8 I.E.=1; // enable control of signal changes to

_ CN10 I.E.=1; // corresponding outputs

_ CN17 I.E.=1; // if the signal changes on them, then

_ CN19 I.E.=1; // interrupt flag _CNIF is set

_ CNIE=1; // enable interrupt INT1

void __ attribute__((__ interrupt__)) _ CNInterrupt()

state=1; // this is emergency mode

_ CNIF=0; // reset the interrupt flag when the signal changes

void main (void)

{ static long int i;

init();

state=0; // we assume that the operating mode at startup is normal

while(1) // start an endless loop

{ if (state) // if emergency mode, then

{ _ CNIE=0; // disable interrupt when signal changes

_ R.A.8=0;

_ R.A.0=1; // in emergency mode

for(i=0; i<210000; i++) //provide delay

state=0; // activate normal engine operation

_ CNIE=1; // enable CN interrupts

{ _ R.A.8=1; // in normal mode

_ R.A.0=0; // provide the direction of rotation of the engine

} // while(1)

3.2. External interruptINT

If you need your microcontroller to respond immediately to the actions of external devices, then the INT interrupt is what you need. The dsPIC33FJ32GP204 microcontroller has three INT channels (INT0, INT1, INT2). That is, you can provide your own interrupt for each of the three external devices. This interrupt is good because it can wake the controller from SLEEP mode. In addition, you do not need to continuously scan these inputs, which would consume microcontroller resources.

An INT interrupt occurs when the input signal changes either “0” -> “1” or “1” -> “0”. It depends on the state of the bit _INT1EP. If _INT1EP=1, then on the falling edge; If _INT1EP=0, then along the leading edge (for example _INT1EP=1 – INT0 interrupt occurs on a falling edge).

In terms of priority, the INT0 interrupt has highest priority, and in the interrupt table it is the very first. Below are the INT1 and INT2 interrupts.

In principle, these are all the features of this interrupt. Everything else is the same as for other interrupts, i.e. you need to enable the corresponding external interrupt. And if an interrupt occurs, it will set the corresponding _INTхIF flag (for example _INT1IF). Don't forget to reset it. In general, everything is as simple as shelling pears.

Let's move on to an example

We issue electronic call to an apartment or house. When you press the button, the device should issue sound signal and wink with light (for those who like to listen to music loudly).

We are drawing up a circuit in PROTEUS; in addition to the microcontroller, we will need a button, a beeper and an LED.

I think everything is very clear in the picture. Let's move on to the program.

#include"p33Fxxxx. h"

// Set the oscillator tuning bits (HS)

_ FOSCSEL(0 x02);

_ FOSC(0 xE2);

charstate;// "1" - enable the call, "0" - disable the call

voidinit(void);//declare the initialization routine

// ** subroutine initialization **

voidinit(void)

( _CN4PUE=1;//turn on the pull-up resistor at input CN4 (RB0)

AD1PCFGL=0xffff;// all pins as digital I/O

PORTB=0x00;// initialize port B

LATB=0;

TRISB=0x0001;// set RB0 output to input

PORTB=0x00;

// initializing port C.

PORTC=0;

LATC=0;

TRISC=0;//set all pins as output

PORTC=0;

RPINR0=0x0000;// the INT1 signal is configured to remove from the RP0 (RB0) pin (this

// command not for all dsPIC

_INT1EP=1;// INT1 interrupt occurs on falling edge

_INT1IE=1;// enable interrupt INT1

// ******* interrupt handling subroutine *

void __ attribute__((__ interrupt__)) _ INT1 Interrupt()

state=1; // call must be enabled

_ INT1 IF=0; // reset interrupt flag INT1

// **** Entry point to the program *

void main (void)

{ static long int i; //declare a variable to organize a delay

init();// call the initialization subroutine

state=0;// first the call must be turned off

while(1)// start an endless loop

( if (state)// if state is "1", then

( _RC0=1;// light up the LED

_RC2=1;// turn on the beeper

for(i=0;i<160000;i++) // delay, ensures a certain playing time

state=0;// indicate that the beeper should be turned off

else// otherwise, if state is "0", then

( _RC0=0;// turn off the LED

_RC2=0;// stop beeping

} // while(1)

Work similarly with interrupts INT0 and INT2. In further examples we will use these interrupts more than once.

The priority mechanism (MP) shows which devices need to be serviced first. MP solves the following problems:

Fixes the priority of any program executed by the processor.

Identifies a request from a host with maximum priority.

Allows the program to be interrupted when a high-priority request occurs.

An interrupt service routine interrupt is called a nested interrupt.

Rice. 6.4 Example of CPU operation in nested interrupt mode.

Figure 6.4 shows an example of a nested interrupt:

Before t 1 no salary

t 1 → Salary from VU4

t 2 → Salary from VU3

t 3 → Salary from VU2

t 4 → servicing of VU2 is completed

t 5 → Salary from VU1

t 6 → servicing of VU1 is completed

t 7 → servicing of VU3 is completed

t 8 → servicing of VU4 is completed

Disadvantage: With a high frequency of receipt of POs, the CPU works ineffectively, because A lot of CPU time is spent on processing, restoring processor registers, and moving from one program to another.

You can reduce the frequency of storage by enabling buffer storage.

When assigning VA priorities, the following conditions are taken into account:

The faster the device is, the higher the priority it is given.

The highest priority is assigned to the device from which data cannot be recovered (usually a timer).

In the family of computers Macintosh The program priority is indicated in the second word of the VI.

In the family of computers IBMPC The program priority is set using a special LSI (large integrated circuit) - programmable interrupt controller.

Technical implementation of multi-level nested priority vector interrupts in a computer based on a single main data exchange channel.

Implementation of multi-level VPs in family computersIBM .

For the implementation of multi-level VPs in computers of the family IBM BIS applied Intel 8259A.

Technical characteristics of the Intel 8259a encore.

Number of salary levels = 8.

The number of levels can be expanded to 64 by cascading chips

The PO service mode, priority levels, and WUAs are set programmatically.

Technical implementation of priority vector interrupts in computers with isolated main data exchange channels (family IBMAT): operating modes of the programmable interrupt controller (PIC),

diagram of connecting the control panel to the system highway,

Scheme for connecting the control panel to the system bus of the computer.

Rice. 6.7 Diagram for connecting the control panel to the system bus and the control unit.

Purpose of LSI pins:

D7- D0 – SD pins are used to receive control information from the CPU and transmit status information to the CPU.

A0 – address input, addressing internal registers of the controller (2 addresses).

~ C.S. (chip select) - crystal selection, allows or disables communication between the controller and the system bus.

• ~C.S.= 0 – there is a connection, ~ C.S.= 1 – no connection.

The first control panel uses addresses – 20 h, 21 h.

The second control panel uses addresses – A0 h, A1 h.

~ R.D., ~ WR– input, output (control room signals), connected to the main lines ~ IORand ~IOW.

INT(output) – ZP signal to the CPU.

~INTA (interrupt acknowledge)– RP signal from the CPU.

CAS2, CAS1, CAS0 – cascade bus. For the master interrupt controller these lines are outputs, and for the slave they are inputs.

~ SP/~ EN– indicates the master (1) or slave (0) control panel.

IR0... IR7 – inputs of interrupt requests from the host.

functional composition and software model of the control panel.

The most important characteristics of an interrupt system are interrupt depth and priority. There is a single-level and multi-level interrupt system in a computer. In single-level systems, interrupt processing does not react to signals from other incoming interrupts. Interrupt requests in such systems are satisfied only after the processing of the previously encountered interrupt has been completed. Modern PCs use multi-level systems that allow interruptions of varying depths. The interrupt depth is the maximum number of ISR programs that can interrupt each other. In this case, if the interrupt depth is n, then n subroutines can be interrupted. The depth of possible interruptions depends on the class of tasks being solved and is determined by the organization of the interrupt processing queue. Simultaneously received interrupt requests to the MP interrupt register are processed according to the principle of priority. Interrupts with the highest priority are serviced first. When interrupt requests are received, the corresponding trigger in the interrupt register is set to 1. Before completing the execution of the next command, the MP polls the interrupt register. The order of implementation of interrupt requests is established in the order of priority previously assigned to each type of interrupt. Assigning priority is a complex task that requires taking into account the importance and urgency of servicing certain interrupts. Typically, power management and machine error interrupts have the highest priority.

Interrupting ISR routines is called interrupt nesting. To organize nested interrupts in each interrupt service routine, you must perform:

1. enable interrupt by EI command

2. temporarily remember the priority of the interrupted program

3. load the new current priority into the priority interrupt circuit

4. service this interrupt

5. restore previous priority

6. restore the interrupted program (IRET command)

Hardware interrupts:

Internal (from processor and coprocessor)

External:

Maskable

Unmasked

Software-Called Interrupts

Internal interrupts also include software-called interrupts. Internal MP interrupts are generated when special conditions arise during the execution of the current command (example: division by zero, bit grid overflow, etc.).

Software-called interrupts are executed under the action of the INT command, and in this case the actions of the MP are similar to calling the ISR program, i.e. saving the return address on the stack, transferring control to the specified address, but there are some differences:

A) the interrupt is executed, pushed onto the stack and the IF (interrupt enable) bit in the flags register is reset to 0.

B) instead of the address of the called subroutine, the call argument is the number of the interrupt vector.

B) upon completion of the software-called interrupt procedure, the processor removes from the stack, in addition to the return address, the stored value of the flags register. Software-called interrupts allow you to easily and quickly call procedures from any memory segment without using long-distance calls. For example, the INT3 software interrupt is traditionally used for program debugging purposes to create a breakpoint and is called by a single-byte instruction.

Parameter name	Meaning
Article topic:	Interrupts.
Rubric (thematic category)	Programming

Watchdog timers.

Often, electrical noise produced by surrounding equipment causes the microcontroller to address the wrong address, after which its behavior becomes unpredictable (the microcontroller “goes crazy”). To monitor such situations, watchdog timers are often included in the microcontroller.

This device causes the microcontroller to reset if its contents are not updated within a certain period of time (usually tens of milliseconds to several seconds). If the change in the contents of the program counter does not correspond to the specified program, the watchdog timer modification command will not be executed. In this case, the watchdog timer resets the microcontroller, setting it to its original state.

Many developers do not use watchdog timers in their applications because they do not see the critical importance of using them to combat the effects of electrical noise, for example, when placing the microcontroller in a cathode ray display close to or near a flyback transformer. ignition coils in a car. In modern electronics, the likelihood of electrical disturbances occurring is negligible, although they sometimes occur in situations similar to those listed above.

It is not recommended to use a watchdog timer to mask software problems. Although this timer can reduce the likelihood of software errors, it is unlikely to eliminate all possible causes of their occurrence. Instead of relying on hardware to prevent software failures, it is better to test the software more thoroughly in different situations.

Many users believe that interrupts are a piece of hardware that is best left alone, as their use requires superior knowledge of the processor to design the interrupt routine. Otherwise, when an interrupt occurs, the system “falls asleep” or “goes crazy”. This feeling usually appears to a developer after experience with interrupts for a personal computer, which has a number of features that complicate the creation of an interrupt handler. Many of these problems do not occur in microcontroller-based hardware. The use of interrupts in this equipment can significantly simplify its development and use.

If you have never dealt with interruptions, then you will have a question - what is it? In a computer system, an interrupt is the execution of a special routine (called an interrupt handler or interrupt service routine) that is called by a hardware signal. During the execution of this subroutine, the implementation of the current program stops. The term “interrupt request” is used because sometimes a program refuses to acknowledge an interrupt and execute the interrupt handler immediately (Figure 2.19).

Interruptions in a computer system are similar to interruptions in everyday life. A classic example of such an interruption is a phone call while watching a television program. When the phone rings, you have three options. The first is to ignore the call. The second is to answer the call, but say that you will call back later. The third is to answer the call, putting aside all current affairs. The computer system also has three similar responses that can be used in response to an external hardware request.

The first possible response - “do not respond to the interrupt until the current task is completed” - is implemented by disabling (masking) servicing the interrupt request. After the task is completed, one of two options is possible: resetting the mask and enabling maintenance, which will lead to calling the interrupt handler, or analyzing the value of the bits ("polling"). indicating the receipt of interrupt requests and direct execution of the service program without calling the interrupt handler. This method of interrupt handling is used when it is necessary to ensure the specified execution time of the main program, since any interruption can disrupt the implementation of an extremely important interface.

Rice. 2.18 - Executing an interrupt.

It is not recommended to mask interrupts for a long time, since during this time several interrupt events may overlap, and only one will be recognized. The permissible duration of masking depends on the specific application of the microcontroller, the type and frequency of such events. It is not recommended to disable interrupts for more than half the minimum expected period of events requesting interrupts.

The interrupt handler always provides the following sequence of actions:

2. Reset the interrupt controller and the equipment that caused the request.

3. Process the data.

4. Restore the contents of the context registers.

5. Return to the interrupted program.

Context registers are registers that determine the current execution state of the main program. Typically these include a program counter, status registers, and accumulators. Other processor registers, such as index registers, are used during interrupt processing, so their contents are also critical to preserve. All other registers are specific to a particular microcontroller and its application.

Once reset, the interrupt controller is ready to accept the next request, and the interrupt-causing equipment is ready to send the request when the appropriate reasons arise. If a new interrupt request arrives, the processor's interrupt masking register will prevent the interrupt from being processed, but the interrupt status register will capture the request, which will await service. After processing of the current interrupt is completed, the interrupt mask will be reset, and the newly received request will be processed.

Nested interrupts are difficult to implement on some types of microcontrollers that do not have a stack. These interrupts can also cause stack overflow problems. The overflow problem is relevant to microcontrollers due to the limited capacity of their data memory and stack: a sequence of nested interrupts can result in more data being pushed onto the stack than is allowed.

Finally, the interrupt is processed. The second TV example shows that you can quickly respond to an interrupt request by accepting the necessary data, which will then be used after solving the current task. In microcontrollers, this is implemented by storing incoming data in a memory array and then processing it when the execution of the original program is completed. This maintenance method is a good compromise between immediately handling the interrupt completely, which may take a long time, and ignoring the interrupt, which may result in losing information about the event that caused the interrupt.

Restoring the context registers and executing the interrupt return instruction returns the processor to the state it was in before the interrupt occurred.

Let's look at what happens to the contents of various registers when an interrupt is processed. The contents of the status register are usually automatically saved along with the contents of the program counter before the interrupt is processed. This eliminates the critical need to store it in memory programmatically using transfer instructions, and then restore it when returning to the original program. However, such automatic saving is not implemented in all types of microcontrollers; therefore, special attention should be paid to the organization of interrupt processing.

If the contents of the status register are saved before the interrupt handler starts executing, then the return command automatically restores it.

If the contents of other processor registers change during interrupt service, they must also be stored in memory before the change and restored before returning to the main program. It is common practice to save all processor registers to avoid unpredictable errors that are very difficult to localize.

The address that is loaded into the program counter when moving to the interrupt handler is usually called the “interrupt vector”. There are several types of vectors. The address that is loaded into the program counter when the microcontroller is started (reset) is usually called the “reset vector”. Different interrupts have different vectors, which relieves the maintenance program of the critical need to determine the cause of the interrupt. The use of one vector by different interrupts usually does not cause problems when operating microcontrollers, since most often the microcontroller executes one single program. This distinguishes a microcontroller from a personal computer, during the operation of which various interrupt sources can be added. (If you have ever connected two devices to the COM1 and COM3 ports, then you have an idea of ​​what we are talking about). In a microcontroller where the hardware is well known, there should not be any problem sharing interrupt vectors.

The last thing left to consider is software interrupts. There are processor instructions that can be used to simulate hardware interrupts. The most obvious use of these instructions is to call system routines that are located in an arbitrary memory location, or require intersegment jumps to access them. This feature is implemented in the Intel i86 family of microprocessors and is used in the BIOS (Basic Input/Output System) and DOS operating system of personal computers to call system routines without the critical need to fix the entry point. Instead, various interrupt vectors are used to select the instruction to be executed when such a software interrupt occurs.

Perhaps after reading this chapter the interrupt mechanism will become more clear to you, or vice versa. You will only get more confused. As each microcontroller is described, it will be shown how the use of interrupts can simplify its use.

Interrupts. - concept and types. Classification and features of the "Interruptions" category. 2017, 2018.