Logic elements of kmop transistors. Element base of various logics: circuits, ttl, ttlsh, kmop

Integrated circuits of transistor-transistor logic are microassemblies with a low degree of integration, built on bipolar transistors. Their main disadvantage is the small number per chip, as well as the criticality of the supply voltage and a fairly large current consumption.

The diagram just above shows a simple logic element - 3I - NOT. It is based on a conventional bipolar multi-emitter transistor VT1. A logic zero level at its output will appear if there are high levels on all three emitters at the same time. VT2 takes on the inverting function (NOT element), and multi-emitter VT1 is a 3I logic element.

Despite the listed disadvantages, the most popular TTL series, K155, is extremely popular today, look at how many homemade radios can be assembled on.

The K155 series is the largest TTL series. It contains more than 100 microassemblies that perform various logical functions and operations (AND, OR, NOT, AND - NOT, OR - NOT, flip-flops, registers, counters, adders.

The logical one level in the microcircuits of this TTL series lies in the voltage range from 2.4 V to 5 V), and the logical zero level is no more than 0.4 V.

Almost all microassemblies in this series are produced in a standard 14-pin package. With a dot or key notch indicating the first terminal. The 7th pin is the body or minus. 14 lying opposite the first is a plus.

The next step in the evolution of the K155 was the K555 series, in which the basic TTL principle was retained, but the collector junctions of the transistors were added. Therefore, the K555 series was called TTLSH (TTL and Schottky diode). In TTLSH, the power consumption decreased by about 2 times, and the performance increased sharply.

CMOS chips

The letter K at the beginning of the abbreviation stands for - complementary. In practice, this means that the microassembly uses pairs with the same parameters, but one transistor has an n-type gate, and the other, respectively, a p-type. They are also called CMOS (Complementary Metal-Oxide Semiconductor).

The figure shows an example of a classic basic NOT gate. That is, if a unit comes to the input, then the output will be a logical zero and vice versa.

Element 2I – NOT. From a couple of these logical elements it is easy to obtain, and from several flip-flops - a counter, a register and an elementary storage device.

And now about the fly in the ointment: at the maximum operating frequency, CMOS elements are noticeably inferior to other logic based on bipolar transistors (TTL) and they are freaking sensitive to static electricity.

Microcircuits based on KMDP structures

Digital ICs based on CMOS structures are increasingly used in the development of a variety of electronic circuits, for which there are very good reasons. KMDP ICs are highly versatile and easily used devices that have unique properties not typical for other classes of digital ICs.

These ICs are called complementary because they are made on the basis of CMOS transistors, i.e. based on pairs of field-effect transistors with the structure: metal - oxide (dielectric) - semiconductor, having very similar characteristics and channels of different types of conductivity. ICs built on this principle consume significantly less power from the power source than all other ICs and can operate in a wider range of supply voltage levels. Electronic wristwatches and automobile devices, medical electronic devices, television receivers, portable calculators are just a few examples of devices that use CMDP ICs.

The main advantages of digital ICs based on CMOS structures are the high input resistance of transistors (Rin) 10 12 Ohms) and a high level of integration. When implementing pulsed devices on integrated CMOS logic elements, the resistance of the timing resistors due to the high input resistances of the transistors is not limited from above; therefore, to obtain pulses with a long duration, the electrical capacitance of the timing capacitors should not be increased.

Complementary structures are complementary pairs of bipolar (p-n-p and n-p-n) or MIS (p-channel and n-channel) transistors, which can significantly improve the performance of ICs. They are fabricated on a common substrate in pockets isolated from the substrate either by a pn junction or a dielectric film. Complementary transistors are made in the form of horizontal and vertical structures.

In transistors with a horizontal structure, the emitter, base, and collector are located on the same horizontal plane, so minority carriers injected into the base do not move perpendicular to the surface of the crystal, but along it. Such transistors are called end (lateral). In the manufacture of end

p-n-p transistors - the formation of emitters is carried out during the basic diffusion of n-p-n - transistors. Then, through a second base diffusion, the emitter of the pnp transistor is surrounded by the collector. The base of the transistor is the original layer of n-type semiconductor between these regions. The width of the base, and therefore the value of the base current transfer coefficient, are determined by the distance between the windows etched in photo mode for the emitter and collector.

In vertical structures, the base is located under the emitter (the injected minority carriers move in a direction perpendicular to the surface of the crystal). All three regions of the pnp transistor (collector, base and emitter) are formed by diffusion. Such complementary structures are difficult to manufacture due to high precision requirements for the concentration of dopant impurities. However, transistors manufactured using this technology have a greater base current transfer coefficient than transistors with a horizontal structure and a high breakdown voltage of the collector junction.

Logic CMOS (CMOS) inverters

Microcircuits based on complementary MOS transistors (CMOS microcircuits) are built on the basis of MOS transistors with n- and p-channels. The same input potential opens an n-channel transistor and closes a p-channel transistor. When a logical one is formed, the upper transistor is open and the lower one is closed. As a result, no current flows through the CMOS circuit. When a logical zero is formed, the lower transistor is open and the upper one is closed. And in this case, no current flows from the power source through the microcircuit. The simplest logical element is an inverter.

an inverter made on complementary MOS transistors is shown in Figure 1.

Figure 1. Schematic diagram of an inverter made on complementary MOS transistors (CMOS inverter)

As a result of this feature of CMOS microcircuits, they have an advantage over the previously discussed types - they consume current depending on the clock frequency applied to the input. An approximate graph of the current consumption of a CMOS chip depending on its switching frequency is shown in Figure 2

Logic CMOS (CMDP) gates "AND"

Logic element diagram "NAND" on CMOS chips practically coincides with the simplified “AND” circuit on electronically controlled switches, which we examined earlier. The difference is that the load is connected not to the common wire of the circuit, but to the power source. A schematic diagram of a “2I-NOT” logic element made on complementary MOS transistors (CMOS) is shown in Figure 3.

Figure 3. Schematic diagram of a 2I-NOT logic element made on complementary MOS transistors (CMOS)

In this circuit, it would be possible to use an ordinary one in the upper arm, however, when generating a low signal level, the circuit would constantly consume current. Instead, p-MOS transistors are used as the load. These transistors form an active load. If it is necessary to generate a high potential at the output, then the transistors open, and if it is low, then they close.

In the circuit of the logical CMOS “AND” element shown in Figure 2, the current from the power supply to the output of the CMOS microcircuit will flow through one of the transistors if at least one of the inputs (or both at once) has a low potential (logic level zero). If a logical one level is present at both inputs of the logical CMOS “AND” element, then both p-MOS transistors will be closed and a low potential will form at the output of the CMOS microcircuit. In this circuit, as well as in the circuit shown in Figure 1, if the transistors of the upper side are open, then the transistors of the lower side will be closed, therefore, in a static state, the CMOS chip will not consume current from the power supply.

A schematic representation of a CMOS 2NAND gate is shown in Figure 4, and the truth table is given in Table 1. In Table 1, the inputs are designated x 1 and x 2, and the output is F.

Figure 4. Symbolic graphical representation of the logical element "2AND-NOT"

Table 1. Truth table of a CMOS chip performing "2NAND"

x1	x2	F
0	0	1
0	1	1
1	0	1
1	1	0

"OR", made on CMOS transistors, is a parallel connection of electronically controlled switches. The difference from the simplified “2OR” circuit discussed earlier is that the load is connected not to the common wire of the circuit, but to the power source. Instead of a resistor, p-MOS transistors are used as a load. A schematic diagram of a “2OR-NOT” logic element made on complementary MOS transistors is shown in Figure 5.

Figure 5. Schematic diagram of a logic element "OR-NOT", made on complementary MOS transistors

The CMOS 2OR-NOT gate circuit uses p-MOS transistors connected in series as the load. In it, current from the power source will flow to the output of the CMOS microcircuit only if all transistors in the upper side are open, i.e. if a low potential () is present at all inputs at once. If at least one of the inputs has a logical one level, then the upper arm of the push-pull stage assembled on CMOS transistors will be closed and no current from the power source will flow to the output of the CMOS microcircuit.

The truth table of the logical element "2OR-NOT", implemented by a CMOS microcircuit, is shown in Table 2, and the graphical designation of these elements is shown in Figure 6.

Figure 6. element "2OR-NOT"

Table 2. Truth table of a MOS chip performing the logical function "2OR-NOT"

x1	x2	F
0	0	1
0	1	0
1	0	0
1	1	0

Currently, it is CMOS microcircuits that have received the greatest development. Moreover, there is a constant tendency to reduce the supply voltage of these microcircuits. The first series of CMOS microcircuits, such as K1561 (a foreign analogue of C4000V) had a fairly wide range of supply voltage changes (3..18V). In this case, when the supply voltage of a particular microcircuit decreases, its maximum operating frequency decreases. Subsequently, as production technology improved, improved CMOS chips with better frequency properties and lower supply voltage appeared, for example, SN74HC.

Features of the use of CMOS chips

The first and main feature of CMOS chips is the high input impedance of these chips. As a result, any voltage can be induced at its input, including one equal to half the supply voltage, and stored at it for quite a long time. When half the power is supplied to the input of a CMOS element, the transistors open in both the upper and lower arms of the output stage, as a result the microcircuit begins to consume an unacceptably large current and may fail. Conclusion: The inputs of digital CMOS chips should never be left unconnected!

The second feature of CMOS chips is that they can operate when the power is turned off. However, they most often work incorrectly. This feature is related to the design of the input stage. The complete circuit diagram of the CMOS inverter is shown in Figure 7.

Figure 7. Complete circuit diagram of CMOS inverter

Diodes VD1 and VD2 were introduced to protect the input stage from breakdown by static electricity. At the same time, when a high potential is applied to the input of a CMOS microcircuit, it will go through the diode VD1 to the power bus of the microcircuit, and since it consumes a sufficiently small current, the CMOS microcircuit will begin to work. However, in some cases this current may not be enough to power the microcircuits. As a result, the CMOS chip may not operate properly. Conclusion: If the CMOS chip is not working properly, carefully check the power supply to the chip, especially the housing terminals. If the negative power terminal is poorly soldered, its potential will differ from the potential of the common wire of the circuit.

The fourth feature of CMOS microcircuits is the flow of pulsed current through the power circuit when it switches from zero to one state and vice versa. As a result, when switching from TTL microcircuits to CMOS analogue microcircuits, the noise level sharply increases. In some cases, this is important, and it is necessary to abandon the use of CMOS microcircuits in favor of BICMOS microcircuits.

Logic levels of CMOS chips

The logic levels of CMOS chips are significantly different from . In the absence of load current, the voltage at the output of the CMOS chip coincides with the supply voltage (logical level of one) or with the potential of the common wire (logical level of zero). As the load current increases, the logical unit voltage can decrease to 2.8V (U p =15V) from the supply voltage. The permissible voltage level at the output of a digital CMOS microcircuit (K561 microcircuit series) with a five-volt power supply is shown in Figure 8.

Figure 8. Logic signal levels at the output of digital CMOS chips

As mentioned earlier, the voltage at the input of a digital chip compared to the output is usually allowed within large limits. For CMOS chips, we agreed on a 30% margin. The boundaries of the logical zero and one levels for CMOS microcircuits with a five-volt supply are shown in Figure 9.

Figure 9. Logic signal levels at the input of digital CMOS chips

When the supply voltage is reduced, the boundaries of logical zero and logical one can be determined in the same way (divide the supply voltage by 3).

CMOS IC Families

The first CMOS chips did not have protection diodes at the input, so their installation presented significant difficulties. This is a family of K172 series chips. The next improved family of CMOS chips, the K176 series, received these protection diodes. It is quite common today. The K1561 series completes the development of the first generation of CMOS chips. In this family, a speed of 90 ns and a supply voltage range of 3 ... 15 V were achieved. Since foreign equipment is currently widespread, I will give a foreign analogue of these CMOS microcircuits - C4000B.

A further development of CMOS chips was the SN74HC series. These microcircuits have no domestic analogue. They have a speed of 27 ns and can operate in the voltage range 2 ... 6 V. They coincide in pinout and functional range with, but are not compatible with them in logical levels, so CMOS microcircuits of the SN74HCT series were developed at the same time (the domestic analogue is K1564) compatible with TTL microcircuits and logical levels.

At this time, there was a transition to three-volt power supply. CMOS microcircuits SN74ALVC with a signal delay time of 5.5 ns and a power range of 1.65 ... 3.6 V were developed for it. The same microcircuits are capable of operating with a 2.5 V power supply. The signal delay time increases to 9 ns.

The most promising family of CMOS chips is currently considered to be the SN74AUC family with a signal delay time of 1.9 ns and a power supply range of 0.8 ... 2.7 V.

The abbreviation CMOS stands for Complementary MOSFET. The abbreviation COSMOS is also sometimes used, which stands for "complementary symmetrical MOS structure". Logic elements of this subfamily are built on both “-channel MOS field-effect transistors and /^-channel MOS field-effect transistors. The patterns of this subfamily are characterized by pronounced symmetry. When developing circuits, only self-turning MOSFETs are used (see Boit, Electronics, part 2, section 8.2, MOSFETs).
The symmetry of the circuits is visible especially well in the circuit of the NOT element (Fig. 6.91). If the I-level is active at input A, for example +5 V, then transistor T2 is unlocked. At its source and substrate there is 0 V. The gate-to-source voltage UGS is +5 V. +5 V is applied to the source and substrate of the Tx transistor.

If +5 V is also applied to the control electrode, then the gate-source voltage UGS = 0 V. The Tx transistor is locked. If Tx is locked and T2 is open, then the output of element Z has level L (Fig. 6.92).
If the i-level O V is active at input A, then transistor T2 is turned off and the gate-to-source voltage UGS is O V. The gate-to-source voltage of transistor Tu UGS = -5 V, since the source voltage is +5 V and the gate voltage is O V. The transistor is unlocked. If Tx is open and T2 is locked, the output of element Z is at level H.
In a CMOS NON element, one transistor is always on and the other is off.
If the output of the element is NOT at level 0, then the element practically does not consume current, since Tx is locked. If level H is NOT active at the output of the element, then the element also consumes virtually no current, since T2 is now locked. To control series-connected elements, no current is also required, since field-effect transistors consume virtually no power. Only during switching is a small current consumed from the power supply, since both transistors are simultaneously but briefly open. One of the transistors goes from open to off and is not yet completely off, and the other is from off to open and is not yet completely open. The transistor capacitors must also be recharged.
All CMOS elements are designed so that in the current branch one transistor is closed and the other is open. The power consumption of CMOS elements is extremely low. It depends mainly on the number of switches per second or switching frequency.
CMOS elements have low power consumption.
In Fig. Figure 6.93 shows the following typical CMOS circuit. If level L is active at both inputs, then transistors 7' and T2 will be open, transistors Tg and T4 will be locked. Tu and T2 with O V on A and B have UGS = - 5 V, and T3 and T4 have UGS = O V. Level H is applied at the Z output.
If at input A there is level H (+5 V), and at input 5 there is level L (O V), then Tu closes and T2 opens. The path from the power supply to the Z output is blocked by an off transistor.

At the same time, transistor T3 is unlocked and approximately 0 V acts at output Z, that is, level L. G4 is locked. Z always has level Z if at least one input has level H. The work table corresponding to the circuit (Fig. 6.93) is shown in Fig. 6.94. The circuit performs an OR-NOT operation with positive logic.
What logical operation is performed by the circuit in Fig. 6.95? First of all, a worksheet must be compiled for the diagram. If Z-levels (O V) are active at both inputs, then transistors T( and T2 open (UGS = - 5 V). Transistors T3 and G4 close (UGS = O V). The output is L-level.
If # levels (+5 V) are active at both inputs, then transistors Tb and T4 open, and transistors Tx and T2 close. The Z output will be set to Z level.
If the I-level is applied to one input and the Z-level to the other, then one of the upper transistors in Fig. 6.95 (7^ or T2) opens. One of the lower ones (T3 or G4) is locked. An if-level will be applied to the output through open transistors. In Fig. Figure 6.96 shows the corresponding truth table. The circuit performs the AND-NOT function in positive logic.

CMOS elements are produced primarily as NAND and NOR elements.
A special element of the CMOS subfamily is the transfer element. It consists of a parallel-connected i-channel MOS transistor and a ^-channel MOS transistor (Fig. 6.97).
The transmission element acts as a switch.
If level H is applied to Gx (for example +5 V) and level L (O V) is applied to G2, then both transistors are turned off. In a channel MOS transistor, a voltage of 0 V is applied between the control electrode and the substrate. The formation of a conducting channel between the source and drain becomes impossible. Also in an i-channel MOS transistor, a voltage of 0 V is applied between the control electrode and the substrate. Here, too, a conducting channel cannot arise. The resistance between points A and Z reaches several hundred MOhms.
If on<7, действует уровень L (О В), а на G2 — уровень Н (+5 В), то напряжение затвора /^-канального МОП-транзистора относительно подложки будет —5 В. Напряжение затвора и-канального МОП-транзистора относительно подложки +5 В. При этих напряжениях образуются проводящие каналы между истоком и стоком. Канал между А и Z будет низкоомным (примерно от 200 Ом до 400 Ом). Рабочая таблица представлена на рис. 6.98.
The levels at the Gl and G2 inputs are always applied in antiphase. Control can occur using the NOT element (Fig. 6.99). This results in a bidirectional key. For field-effect transistors of the transfer element, the source and drain can mutually change their functions. Therefore, the gate output is indicated in the middle of its conventional line (Fig. 6.99).
Integrated CMOS ICs always contain multiple logic elements that can be used individually or as a single complex logic function. In Fig. Figure 6.100 shows the structure of a 4000 A CD circuit. This circuit contains two OR-HE gates with three inputs each and a NOT gate. The CD 4012 A circuit (Fig. 6.101) contains two NAND elements with four inputs each.
Arithmetic logic device integrated circuits contain many CMOS elements. In Fig. Figure 6.102 shows a diagram of a 4-bit shift register. This scheme is discussed in detail in Chap. 8.

Rice. 6.102. CD 4015 A CMOS 4-bit shift register circuit (RCA)

The CD 4008 A chip is a 4-bit full adder. Full adders are discussed in detail in Chap. 10. The circuit is shown here as an example of CMOS circuit design (Fig. 6.103).
CMOS integrated circuits can be manufactured with very high element densities,
You can fit the circuit of an entire calculator into one chip. Further improvement of technology leads to an increase in possible packaging density.
The supply voltage of CMOS elements can fluctuate over a wide range.
For the CD-4000-A series (Fig. 6.100—6.103), the RCA manufacturer indicates the supply voltage range from 3 V to 15 V. Typical transfer characteristics for a range of supply voltages are shown in Fig. 6.104.
Supply voltages are often +5 V and +10 V. For these supply voltages in Fig. Figures 6.105 and 6.106 show level diagrams. Higher supply voltages are characterized by better noise immunity.
The difference between the L and H levels, which is responsible for noise immunity, for CMOS circuits is approximately 30% to 40% of the supply voltage.
The following table shows the most important parameters of CMOS elements:

Rice. 6.103. CD 4008 A CMOS 4-bit Full Adder Circuit (RCA)

Rice. 16.10.

The fundamental difference between CMOS circuits and nMOS technology is the absence of active resistances in the circuit. A pair of transistors with a different type of channel is connected to each input of the circuit. Transistors with a p-type channel are connected by the substrate to the power source, so the formation of a channel in them will occur when the potential difference between the substrate and the gate is sufficiently large, and the potential at the gate must be negative relative to the substrate. This state is ensured by applying ground potential to the gate (i.e. logical 0). Transistors with an n-type channel are connected by the substrate to ground, so the formation of a channel in them will occur when a power source potential is applied to the gate (i.e. logical 1). Simultaneously applying a logical zero or logical one to such pairs of transistors with different types of channels leads to the fact that one transistor of the pair will necessarily be open and the other closed. Thus, conditions are created for connecting the output either to a power source or to ground.

So, in the simplest case, for the inverter circuit (Fig. 16.10) at A = 0, transistor VT1 will be open and VT2 will be closed. Consequently, the output of circuit F will be connected through channel VT1 to the power source, which corresponds to the logical one state: F=1. At A=1, transistor VT1 will be closed (the gate and substrate have the same potentials), and VT2 will be open. Therefore, the output of circuit F will be connected through the channel of transistor VT2 to ground. This corresponds to a logical zero state: F=0.

Logical addition (Fig. 16.11) is carried out by connecting the p-channels of transistors VT1 and VT2 in series. When at least one unit is supplied, a single channel does not form for these transistors. At the same time, thanks to the parallel connection of VT3 and VT4, the corresponding transistor at the bottom of the circuit is opened, ensuring the connection of output F to ground. It turns out F=0 when at least one logical 1 is applied - this is the OR-NOT rule.

Rice. 16.11.

The NAND function is carried out through a parallel connection of VT1 and VT2 in the upper part of the circuit and a serial connection of VT3 and VT4 in the lower part (Fig. 16.12). If zero is applied to at least one input, a single channel on VT3 and VT4 will not be formed, the output will be disconnected from ground. At the same time, at least one transistor in the upper part of the circuit (to the gate of which a logical zero is applied) will provide connection of the output F to the power source: F = 1 when at least one zero is applied - the AND-NOT rule.

Rice. 16.12.

Brief summary

Depending on the element base, there are different IC production technologies. The main ones are TTL on bipolar transistors and nMOS and CMOS on field effect transistors.

Key terms

nMOS technology field effect transistors with an n-type induced channel.

3-state buffer– the output part of the TTL circuit, providing the possibility of transition to the third, high-impedance state.

CMOS technology- IC production technology based on field effect transistors with channels of both types of electrical conductivity.

Open collector– a variant of implementing the buffer part of TTL elements without a resistor in the load circuit, which is removed outside the circuit.

Resistive Load Circuits– TTL circuits in which the state of the buffer circuit is determined by the state of not one, but two transistors.

Transistor-transistor logic– technology for the production of ICs based on bipolar transistors.

Accepted abbreviations

CMOS – complementary, metal, oxide, semiconductor

Practice kit

Exercises for lecture 16

Exercise 1

Option 1 for exercise 1.Draw a circuit of a 3-input NOR element using nMOS technology.

Option 2 for exercise 1.Draw a circuit of a 3-input NAND element using nMOS technology.

Option 3 for exercise 1.Draw a circuit of a 4-input NOR element using nMOS technology.

Exercise 2

Option 1 for exercise 2.Draw a circuit of a 3-input NOR gate using CMOS technology.

Option 2 for exercise 2.Draw a circuit of a 3-input NAND gate using CMOS technology.

Option 3 for exercise 2.Draw a circuit of a 4-input NOR gate using CMOS technology.

Exercise 3

Option 1 for exercise 3.Draw a circuit of a 3-input NOR element using TTL technology.

Option 2 for exercise 3.Draw a diagram of a 3-input NAND element using TTL technology.

Option 3 for exercise 3.Draw a circuit of a 4-input NOR element using TTL technology.

Exercise 4

Option 1 for exercise 4.Draw a circuit of a 3-input OR element using nMOS technology.

Option 2 for exercise 4.Draw a circuit of a 3-input AND element using nMOS technology.

Option 3 for exercise 4.Draw a circuit of a 4-input OR element using nMOS technology.

Exercise 5

Option 1 for exercise 5.Draw the circuit of a 3-input OR gate using CMOS technology.

Option 2 for exercise 5.Draw a circuit diagram of a 3-input AND element using CMOS technology.

Option 3 for exercise 5.Draw the circuit of a 4-input OR gate using CMOS technology.

Exercise 6

Option 1 for exercise 6.Draw a circuit of a 3-input OR element using TTL technology.

Option 2 for exercise 6.Draw a circuit of a 3-input AND element using TTL technology.

Option 3 for exercise 6.Draw a circuit of a 4-input OR element using TTL technology.

Exercise 7

Option 1 for exercise 7.Draw a diagram of a 2I-OR-NOT element using TTL technology.

Option 2 for exercise 7.Draw a diagram of a 2I-OR-NOT element using CMOS technology.

Option 3 for exercise 7.Draw a diagram of a 2AND-OR-NOT element using nMOS technology.

Exercise 8

Option 1 for exercise 8.Draw a circuit of a 3-input NOR gate with a 3-state buffer.

Option 2 for exercise 8.Draw the circuit of a 3-input NAND gate with an open collector.

Option 3 for exercise 8.Draw a circuit of a 3-input OR gate with a 3-state buffer.

INTRODUCTION

Let's talk about the characteristics of an ideal family of logic chips. They must dissipate no power, have zero propagation delay, controllable signal rise and fall times, and have noise immunity equivalent to 50% of the output signal swing.

The parameters of modern families of CMOS chips (complementary MOS) are approaching these ideal characteristics.

First, CMOS chips dissipate low power. Typical static power dissipation is on the order of 10 nV per valve, which is generated by leakage currents. Active (or dynamic) power dissipation depends on the power supply voltage, frequency, output load and input rise time, but its typical value for a single gate at a frequency of 1 MHz and a 50 pF load does not exceed 10 mW.

Secondly, the signal propagation delay time in CMOS gates, although not zero, is quite small. Depending on the power supply voltage, the signal propagation delay for a typical element ranges from 25 to 50 ns.

Third, the rise and fall times are controlled and represent linear rather than step functions. Typically the rise and fall times are 20-40% greater than the propagation delay time.

Finally, a typical noise immunity value approaches 50% and is approximately 45% of the output signal amplitude.

Another important factor in favor of CMOS chips is their low cost, especially when used in portable equipment powered by low-power batteries.

Power supplies in systems built on CMOS chips can be low-power and, as a result, inexpensive. Due to low power consumption, the power subsystem can be simpler and therefore cheaper. There is no need for radiators and fans due to low power dissipation. Continuous improvement of technological processes, as well as an increase in production volumes and expansion of the range of manufactured CMOS microcircuits leads to a reduction in their cost.

There are many series of CMOS logic chips. The first of them was the K176 series, then K561 (CD4000AN) and KR1561 (CD4000BN), but the functional series received the greatest development in the KR1554 (74ACxx), KR1564 (74HCxx) and KR1594 (74ACTxx) series.

The functional series of modern CMOS microcircuits of the KR1554, KR1564 and KR1594 series contain full-function equivalents of the TTLSH series KR1533 (74ALS) and K555 (74LS) microcircuits, which completely coincide both in the functions performed and in the pinout. Modern CMOS microcircuits, compared to their prototypes, the K176 and K561 series, consume significantly less dynamic power and are many times faster in performance.

To simplify circuit solutions, CMOS series with input threshold voltage of TTL levels (KR1594 and some others) and CMOS levels (KR1554, KR1564 and some others) have been developed. The operating temperature range for general purpose microcircuits is -40-+85C, and -55-+125C for special applications. In table Figure 1 shows a comparison of the input and output characteristics of CMOS and TTLSH microcircuits.

Table 1. Comparison of electrical parameters of CMOS and TTL circuits

TECHNOLOGY	CMOS with PCC gate	Improved CMOS with PCC gate	CMOS with metal gate	Standard	Low-consuming TTLSH	Improved Low-Power TTLSh	Fast-acting TTLSH


Power dissipation per gate (mW)
Static
At 100 kHz
Propagation delay time (ns) (CL = 15 pF)
Maximum clock frequency (MHz) (CL = 15 pF)
Minimum output current (mA)
Standard outputs

Output fanout ratio (Load per K555 input)
Standard outputs
Outputs with increased load capacity
Maximum input current, IIL (mA) (VI = 0.4 V)

CHARACTERISTICS OF CMOS CIRCUITS

The purpose of this section is to provide the system designer with the necessary knowledge of how CMOS digital ICs operate and behave when exposed to various control signals. Quite a lot has been written about the design and production technology of CMOS microcircuits, so here we will consider only the circuit design features of microcircuits of this family.

The basic CMOS circuit is the inverter shown in Fig. 1. It consists of two field-effect transistors operating in enrichment mode: with a P-type channel (upper) and an N-type channel (lower). The power pins are designated as follows: VDD or VCC for the positive pin and VSS or GND for the negative pin. The designations VDD and VCC are borrowed from conventional MOS circuits and symbolize the source and drain power supplies of the transistors. They do not apply directly to CMOS circuits, since the power pins are the sources of both complementary transistors. The designations VSS or GND are borrowed from TTL circuits, and this terminology is retained for CMOS chips. Next, the designations VCC and GND will be indicated.

The logic levels in a CMOS system are VCC (logical “1”) and GND (logical “0”). Because the current flowing in the “on” MOSFET creates virtually no voltage drop across it, and because the input resistance of the CMOS gate is very high (the input characteristic of the MOSFET is mainly capacitive and looks similar to the current-voltage characteristic of a 1012 Ohm MOSFET , shunted by a 5 pF capacitor), then the logic levels in the CMOS system will be almost equal to the voltage of the power supply.

Now let's look at the characteristic curves of MOSFETs to get an idea of how rise and fall times, propagation delays, and power dissipation will change with changing power supply voltage and load capacitance.

In Fig. Figure 2 shows characteristic curves of N-channel and P-channel field-effect transistors operating in enrichment mode.

A number of important conclusions follow from these characteristics. Consider the curve for an N-channel transistor with a Gate-Source voltage equal to VGS = 15 V. It should be noted that for a constant control voltage VGS, the transistor behaves as a current source for values of VDS (Drain-Source voltage) greater than VGS-VT (VT is the threshold voltage of the MOSFET). For values of VDS less than VGS-VT, the transistor behaves essentially like a resistor.

It should also be noted that for smaller values of VGS the curves are similar, except that the IDS value is much smaller and, in fact, the IDS increases with the square of the VGS. The P-channel transistor has almost identical, but complementary (complementary) characteristics.

In the case of driving a capacitive load using CMOS elements, the initial change in voltage applied to the load will be linear, due to the “current” characteristic in the initial section, obtained by rounding off the predominant resistive characteristic when the VDS value differs little from zero. In relation to the simplest CMOS inverter shown in Fig. 1, as VDS decreases to zero, the output voltage VOUT will tend to VCC or GND, depending on whether the transistor is P-channel or N-channel.

If VCC, and therefore VGS, is increased, the inverter must develop a larger voltage amplitude across the capacitor. However, for the same voltage increment, the load capacity of the IDS increases sharply as the square of VGS, and therefore the rise times and propagation delays shown in Fig. 3, decrease.

Thus, it can be seen that for a given design, and therefore a fixed value of load capacitance, increasing the power supply voltage will increase system performance. Increasing VCC will increase performance, but also power dissipation. This is true for two reasons. Firstly, the product CV2f, and therefore the power, increases. This is the power dissipated in a CMOS circuit, or any similar circuit for the reason stated above, when driving a capacitive load.

For specified values of load capacitance and switching frequency, power dissipation increases in proportion to the square of the voltage drop across the load.

The second reason is that the VI product or power dissipated in a CMOS circuit increases as the power supply voltage VCC increases (for VCC>2VT). Each time the circuit switches from one state to another, there is a momentary through current flowing from VCC to GND through two simultaneously open output transistors.

Since the threshold voltages of the transistors do not change with increasing VCC, the input voltage range within which the upper and lower transistors are simultaneously in a conducting state increases with increasing VCC. At the same time, a larger value of VCC provides larger values of control voltages VGS, which also lead to an increase in JDS currents. Due to this, if the rise time of the input signal was zero, then there would be no through current through the output transistors from VCC to GND. These currents arise because the edges of the input signal have finitely small rise and fall times, and therefore the input voltage requires a certain finitely small time to pass through the range in which the two output transistors are turned on simultaneously. Obviously, the rise and fall times of the input signal edges should be minimal to reduce power dissipation.

Let's take a look at the transfer characteristics (Fig. 5) and how they change with the supply voltage VCC. Let's agree to assume that both transistors in our simplest inverter have identical, but complementary characteristics and threshold voltages. Assume that the threshold voltages, VT, are 2V. If VCC is less than the 2V threshold voltage, none of the transistors can be turned on and the circuit will not work. In Fig. Figure 5a shows a situation where the power supply voltage exactly matches the threshold voltage. In this case, the circuit should operate with 100% hysteresis. However, this is not exactly hysteresis, since both output transistors are turned off and the output voltage is maintained across the gate capacitances downstream of the circuits. If VCC is within one and two threshold voltages (Fig. 5b), the amount of “hysteresis” decreases as VCC approaches a value equivalent to 2VT (Fig. 5c). At a VCC voltage equivalent to two threshold voltages, there is no “hysteresis”; there is also no through current through two simultaneously open output transistors during switching moments. When the VCC value exceeds two threshold voltages, the transfer characteristic curves begin to round off (Fig. 5d). When VIN passes through a region where both transistors are open, i.e. in the conducting state, the currents flowing in the channels of the transistors create voltage drops, giving a rounding of the characteristics.

When reviewing a CMOS system for noise, there are at least two characteristics to consider: noise immunity and noise margin.

Modern CMOS circuits have a typical noise immunity value of 0.45VCC. This means that a false input signal equal to 0.45VCC or less different from VCC or GND will not propagate through the system as a faulty logic level. This does not mean that no signal will appear at the output of the first circuit. In fact, as a result of exposure to the interference signal, an output signal will appear at the output, but it will be weakened in amplitude. As this signal propagates through the system, it will be weakened further by subsequent circuits until it disappears completely. Typically, such a signal does not change the output state of the logic element. In a conventional flip-flop, a false input clock pulse with an amplitude of 0.45VCC will not change its state.

The CMOS chip manufacturer also guarantees a noise immunity margin of 1 Volt over the entire range of supply voltages and temperatures and for any combination of inputs. This is just a deviation of the noise immunity characteristic, for which a special set of input and output voltages is guaranteed. In other words, from this characteristic it follows that in order for the output signal of the circuit, expressed in Volts, to be within 0.1VCC of the value of the corresponding logic level (“zero” or “one”), the input signal must not exceed the value 0. 1VCC plus 1 Volt above ground level or below power level. Graphically this situation is shown in Fig. 4.

These characteristics closely resemble the noise immunity margin of standard TTL circuits, which is 0.4 V (Fig. 6). To complete the picture of the dependence of the output voltage VOUT on the input VIN, we present the transfer characteristics curves (Fig. 5).

ANALYSIS OF APPLICATION IN THE SYSTEM

This section discusses various situations that arise during system development: unused inputs, parallel connection of elements to increase load capacity, wiring of data buses, coordination with logic elements of other families.

UNUSED INPUTS

Simply put, unused inputs should not be left unconnected. Due to the very high input resistance (1012 ohms), the floating input can drift between logic zero and logic one, creating unpredictable circuit output behavior and associated system problems. All unused inputs must be connected to the power bus, “common” wire, or another usable input. The choice is not at all random, since the possible impact on the output load capacity of the circuit should be taken into account. Consider, for example, a four-input 4NAND gate used as a two-input 2NAND logic gate. Its internal structure is shown in Fig. 7. Let inputs A and B be unused inputs.

If unused inputs are to be connected to a fixed logic level, then inputs A and B must be connected to the power rail to enable the remaining inputs to operate. This will turn on the lower A and B transistors and turn off the corresponding upper A and B transistors. In this case, no more than two upper transistors can be turned on at the same time. However, if inputs A and B are connected to input C, the input capacitance triples, but every time input C goes to logic zero, the top transistors A, B, and C turn on, tripling the maximum output current at logic one. . If input D also receives a logical zero level, all four upper transistors are turned on. Thus, connecting unused inputs of an NAND element to the power bus (OR-NOT to the “common” wire) will turn them on, but connecting unused inputs to other used inputs guarantees an increase in the output flowing current of the logical “one” level, in the case of an element AND-NOT (or the output inflowing current at the level of logical “zero”, in the case of an OR-NOT element).

For transistors connected in series, the output current does not increase. Given this circumstance, a multi-input logic element can be used to directly control a powerful load, for example, a relay coil or an incandescent lamp.

PARALLEL CONNECTION OF LOGICAL ELEMENTS

Depending on the type of logic element, combining inputs guarantees an increase in the load capacity for either the leaking or sinking currents, but not both at the same time. In order to guarantee an increase in the two output currents, it is necessary to connect several logic elements in parallel (Fig. 8). In this case, an increase in load capacity is achieved by connecting several chains of transistors in parallel (Fig. 7), thus increasing the corresponding output current.

DATA BUS ROUTING

There are two main ways to do this. The first method is a parallel connection of conventional CMOS buffer elements (for example,). And the second, most preferable, method is to connect elements with three output states.

POWER SUPPLY INTERFERENCE FILTERING

Since CMOS circuits can operate over a wide range of supply voltages (3-15 V), minimal filtering is necessary. The minimum power supply voltage value is determined by the maximum operating frequency of the fastest element in the system (usually a very small part of the system operates at the maximum frequency). Filters should be selected to maintain the supply voltage approximately halfway between the specified minimum value and the maximum voltage at which the microcircuits are still operational. However, if power dissipation is to be minimized, the power supply voltage must be selected as low as possible while still meeting performance requirements.

MINIMIZING SYSTEM POWER DISSIPATION

In order to minimize system power consumption, it must operate at a minimum speed, performing the task at a minimum supply voltage. The instantaneous values of dynamic (AC) and static (DC) power consumption increase, both with increasing frequency and voltage of the power source. Dynamic power consumption (AC) is a function of the product CV2f. This is the power dissipated in the buffer element driving the capacitive load.

It is obvious that dynamic power consumption increases in direct proportion to frequency and is proportional to the square of the power supply voltage. It also increases with load capacitance, which is mainly determined by the system, and is not variable. Static (DC) power consumption is dissipated at switching moments and is the product of VI. In any CMOS element, an instantaneous current arises from the power bus to the “common” wire (at VCC>2VT) Fig. 9.

The maximum current amplitude is a rapidly increasing function of the input voltage, which in turn is a function of the power supply voltage (Fig. 5d).
The actual value of the product VI of the power dissipated by the system is determined by three indicators: the voltage of the power source, the frequency and times of the rising and falling edges of the input signal. A very important factor is the rise time of the input signal. If the rise time is long, the power dissipation increases because the current path is established during the entire time the input signal passes the region between the threshold voltages of the upper and lower transistors. Theoretically, if the rise time was taken to be zero, no current path would occur and VI power would be zero. However, since the rise time is of course small, there is always a through current that increases rapidly with increasing supply voltage.

There is one more circumstance regarding the rise time of the input signal and power consumption. If the circuit is used to drive a large number of loads, the rise time of the output signal will increase. This will increase the VI power dissipation in each device controlled by such a circuit (but not in the control circuit itself). If power consumption reaches a critical value, it is necessary to increase the slope of the output signal by connecting buffer elements in parallel or sharing loads in order to reduce the total power consumption.

Now let's summarize the influence of the effects of power supply voltage, input voltage, rise and fall times of the input signal edges, and load capacitance on power dissipation. The following conclusions can be drawn:

Power supply voltage. The product CV2f of power dissipation increases with the square of the supply voltage. The product VI of power dissipation increases approximately in proportion to the square of the power supply voltage.
Input voltage level. The VI product of power dissipation increases if the input voltage is between “ground potential (GND) plus threshold voltage” and “supply voltage (VCC) minus threshold voltage.” The highest power dissipation occurs when VIN approaches 0.5 VCC. The product CV2f is not affected by the input voltage level.
Rise time of the input signal. The product VI of the power dissipation increases with increasing rise time because the through current through the simultaneously on output transistors is established for a longer time. The product CV2f is also not affected by the rise time of the input signal.
Load capacity. The product CV2f of the power dissipated in the circuit increases in proportion to the load capacitance. The product VI of power dissipation does not depend on the load capacitance. However, an increase in the load capacitance will lead to an increase in the rise times of the edges of the output signal, which, in turn, will lead to an increase in the product VI of the dissipated power in the logic elements controlled by this signal.

COORDINATION WITH LOGIC ELEMENTS OF OTHER FAMILIES

There are two basic rules for matching elements of all other families with CMOS chips. First, the CMOS circuit must provide the necessary input current and voltage requirements for elements of other families. And secondly, and even more importantly, the amplitude of the output signal of other logic gate families must match the voltage of the CMOS circuit's power supply as closely as possible.

P-CHANNEL MOSFET CIRCUITS

There are a number of requirements that must be met when matching P-MOS and CMOS circuits. Firstly, this is a set of power supplies with different voltages. Most P-MOS circuits are designed to operate at voltages between 17 V and 24 V, while CMOS circuits are designed for a maximum voltage of 15 V. Another problem with P-MOS circuits, unlike CMOS, is the significantly lower output amplitude signal than the power supply voltage. The output voltage of P-MOS circuits ranges from essentially the more positive potential of the supply voltage (VSS) to several volts above the more negative potential (VDD). Therefore, even if the P-MOS circuit is running from a 15 V source, its output amplitude will still be less than what is needed to match the CMOS circuit. There are several ways to solve this problem, depending on the system configuration. Let's consider two ways to build a system entirely on MOS circuits and one method when the system uses TTLSH circuits.

The first example uses only P-MOS and CMOS circuits with supply voltages less than 15 V (see Figure 10). In this configuration, the CMOS circuit drives the P-MOS directly. However, a P-MOS circuit cannot drive CMOS directly because its logic zero output voltage is well above the system's zero potential. To “pull up” the output potential of the circuit to zero, an additional resistor RPD is introduced. Its value is chosen small enough to provide the desired RC time constant when switching the output from “one” to “zero” and, at the same time, large enough to provide the required value of the logical “one” level. This method is also suitable for open-drain P-MOS outputs.

Another option in an all-MOS system is to use a conventional zener diode reference voltage to drive a more negative potential to power the CMOS circuit (Figure 11).

This configuration uses a 17-24 V P-MOS power supply. The reference voltage is selected to reduce the CMOS supply voltage to the minimum swing-to-peak output voltage of the P-MOS circuit. The CMOS circuit can still drive the P-MOS directly, but now, the P-MOS circuit can drive the CMOS without a pull-up resistor. Other limitations include the supply voltage of the CMOS circuits, which must be less than 15 V, and the need for the reference to provide sufficient current to power all the CMOS circuits in the system. This solution is quite suitable if the power supply of the P-MOS circuit must be greater than 15 V, and the current consumption of the CMOS circuits is small enough to be provided by a simple parametric regulator.

If the system uses TTLS circuits, there must be at least two power supplies. In this case, the CMOS circuit can operate from a unipolar source and drive the P-MOS circuit directly (Fig. 12).

N-CHANNEL MOSFET CIRCUITS

Matching CMOS with N-MOS circuits is simpler, although some problems exist. First, N-MOS circuits require lower power supply voltages, typically in the range of 5-12 V. This allows them to be matched directly to CMOS circuits. Secondly, the amplitude of the output signal of CMOS circuits ranges from almost zero to the power supply voltage minus 1-2 V.

At higher power supply voltages, N-MOS and CMOS circuits can operate directly because the N-MOS circuit's output logic level will differ from the power supply voltage by only 10-20%. However, at lower supply voltages, the logical unit level voltage will be lower by 20-40%, so it is necessary to include a “pull-up” resistor (Fig. 13).

TTL, TTLSH CIRCUITS

When matching these families with CMOS circuits, two issues arise. First, is the logic-1 level voltage of bipolar families sufficient to drive CMOS circuits directly? TTL and TTLSh circuits are quite capable of driving 74HCXX series CMOS circuits directly without additional pull-up resistors. However, they are not capable of controlling CMOS circuits of the CD4000 series (K561, KR1561), since the characteristics of the latter do not guarantee operation in the case of direct connection without pull-up resistors.

TTL circuits are capable of directly driving CMOS circuits over the entire operating temperature range. Standard TTL circuits are capable of directly driving CMOS circuits over most of the temperature range. However, closer to the lower limit of the temperature range, the logic unit level voltage of TTL circuits decreases and the introduction of a “pull-up” resistor is recommended (Fig. 14).

According to the dependence of the permissible voltage values of the input levels on the power supply voltage for CMOS circuits (see Fig. 4), if the input voltage exceeds the value of VCC-1.5 V (at VCC = 5 V), then the output voltage will not exceed 0.5 V . The next CMOS element will boost this 0.5V voltage to the corresponding VCC or GND voltage. The logic “1” level voltage for standard TTL circuits is a minimum of 2.4 V with an output current of 400 μA. This is the worst case, since the TTL circuit's output voltage will only approach this value at minimum temperature, maximum input level "0" (0.8 V), maximum leakage currents and minimum supply voltage (VCC = 4.5 V).

Under normal conditions (25°C, VIN = 0.4 V, nominal leakage currents in the CMOS circuit and power supply voltage VCC = 5 V), the logic “1” level will more likely correspond to VCC-2VD or VCC-1.2 V. When the temperature alone changes, the output voltage will change according to the dependence “two times -2 mV per degree temperature” or “-4 mV per degree”. VCC-1.2V is sufficient to directly drive a CMOS circuit without the need for a pull-up resistor.

If, under certain conditions, the output voltage of a logic-1 TTL circuit may fall below VCC-1.5 V, a resistor must be used to drive the CMOS circuit.
The second question is, can a CMOS circuit provide enough output current to provide a logic-0 level input voltage to a TTL circuit? For logical “1” this problem does not exist.

For a TTL circuit, the input current is small enough to drive two such inputs directly. For a standard TTL circuit, the input current is ten times higher than the current of the TTL circuit and, therefore, the output voltage of the CMOS circuit will then exceed the maximum permissible value of the logic “0” level voltage (0.8 V). However, if you carefully examine the output drive specifications of CMOS circuits, you will notice that a two-input NAND gate can drive a single TTL input, albeit only in extreme cases. For example, the output voltage of the logical zero level for the MM74C00 and MM74C02 devices over the entire temperature range is 0.4 V at a current of 360 μA, with an input voltage of 4.0 V and a supply voltage of 4.75 V. Both circuits are shown in Fig. 15.

Both circuits have the same load capacity, but their structures are different. This means that each of the bottom two transistors of the MM74C02 can supply the same current as two MM74C00 transistors in series. Two MM74C02 transistors together can provide twice the current at a given output voltage. If we allow the logic zero output voltage to increase to a value of 0.8 V, then the MM74C02 device will be able to provide four times the output current than 360 μA, i.e. 1.44 mA, which is close to 1.6 mA. In fact, 1.6 mA is the maximum input current for a TTL input, and most TTL circuits operate at no more than 1 mA. Also, 360 µA is the minimum output current for CMOS circuits. The actual value is in the range of 360-540 µA (which corresponds to the input current of 2-3 TTLSH inputs). A current of 360µA is specified for a 4V input voltage. For a 5V input voltage, the output current will be about 560µA across the entire temperature range, making TTL input control even easier. At room temperature and an input voltage of 5 V, the output of the CMOS circuit can provide a current of 800 µA. Therefore, a two-input NOR gate will provide an output current of 1.6 mA at 0.4 V if both inputs of the NOR gate are supplied with 5 V.

From this we can conclude that the single two-input NOR gate included in the MM74C02 can be used to drive a standard TTL input instead of a dedicated buffer. However, this will lead to a slight decrease in noise immunity in the temperature range.

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