DAC elements. Modern digital-to-analog converters DAC

Ministry of Education and Science of Ukraine

Odessa National Maritime Academy

Department of Marine Electronics

in the discipline "Systems for collecting and processing telemetric information"

"Digital-to-analog converters"

Completed:

set of FEM and RE

groups 3131

Strukov S.M.

Checked: Art. teacher

Kudelkin I.N.

Odessa – 2007

1. Introduction

2. General information

3. Serial DACs

4. Parallel DACs

5. Application of DAC

6. DAC parameters

7. List of references

INTRODUCTION

Recent decades have been due to the widespread introduction of microelectronics and computer technology into the national economy, the exchange of information with which is ensured by linear analog and digital converters (ADC and DAC).

The modern stage is characterized by large and ultra-large integrated circuits DACs and ADCs with high performance parameters: speed, small errors, multi-bit. The inclusion of an LSI DAC and ADC as a single, functionally complete unit greatly simplified their implementation in devices and installations used both in scientific research and in industry and made it possible to quickly exchange information between analog and digital devices.

General information

A digital-to-analog converter (DAC) is designed to convert a number, usually defined as a binary code, into a voltage or current proportional to the value of the digital code. The circuitry of digital-to-analog converters is very diverse. In Fig. Figure 1 shows a classification scheme of the DAC according to its circuit characteristics. In addition, ICs of digital-to-analog converters are classified according to the following criteria:

o By type of output signal: with current output and voltage output.

o By type of digital interface: with serial input and with parallel input of the input code.

o By the number of DACs on the chip: single-channel and multi-channel.

o By speed: moderate and high speed.

Rice. 1. DAC classification

SERIAL DACs

DAC with pulse width modulation

Very often, a DAC is part of microprocessor systems. In this case, if high speed is not required, digital-to-analog conversion can be very easily accomplished using pulse width modulation (PWM). The DAC circuit with PWM is shown in Fig. 1a.

Rice. 1. DAC with pulse width modulation

Digital-to-analog conversion is most simply organized if the microcontroller has a built-in pulse-width conversion function (for example, AT90S8515 from Atmel or 87C51GB from Intel). PWM output controls the switch S. Depending on the specified conversion bit depth (for the AT90S8515 controller, 8, 9 and 10 bit modes are possible), the controller, using its timer/counter, generates a sequence of pulses, the relative duration of which g = t And / T is determined by the relation

Where N- conversion bit depth, and D- converted code. A low-pass filter smooths out the pulses, highlighting the average voltage value. As a result, the output voltage of the converter

The considered circuit provides almost ideal linearity of the conversion and does not contain precision elements (except for the reference voltage source). Its main drawback is low performance.

Serial switched capacitor DAC

The PWM DAC circuit discussed above first converts the digital code into a time interval, which is generated using a binary counter quantum by quantum, so to obtain N- 2 bit conversions required N time quanta (cycles). The serial DAC circuit shown in Fig. 2 allows digital-to-analog conversion to be performed in significantly fewer clock cycles.

In this circuit, the capacitor capacities are WITH 1 and WITH 2 are equal. Before the conversion cycle begins, the capacitor WITH 2 is discharged with a key S 4 . The input binary word is specified as a serial code. Its conversion is carried out sequentially, starting from the least significant digit d 0 . Each conversion cycle consists of two half-cycles. In the first half-cycle the capacitor WITH 1 charges to reference voltage U op at d 0 =1 by closing the key S 1 or discharges to zero at d 0 =0 by closing the key S 2. In the second half-cycle with the keys open S 1 ,S 2 and S 4 key closes S 3, which causes the charge to divide in half between WITH 1 and WITH 2. As a result we get

U 1 (0)=U out (0)=( d 0 /2)U op

While on the capacitor WITH 2 charge is maintained, capacitor charging procedure WITH 1 must be repeated for the next digit d 1 input word. After a new recharge cycle, the voltage on the capacitors will be

The transformation is performed in the same way for the remaining bits of the word. As a result for N-bit DAC output voltage will be equal to

If you want to save the result of the conversion for any long time, a UVH should be connected to the output of the circuit. After the end of the conversion cycle, you should carry out a sampling cycle, switch the UVH to storage mode and start the conversion again.

Thus, the presented circuit transforms the input code in 2 N quanta, which is significantly less than that of a PWM DAC. Here, only two matched small capacitors are required. The configuration of the analog part of the circuit does not depend on the bit depth of the converted code. However, in terms of performance, a serial DAC is significantly inferior to parallel digital-to-analog converters, which limits its scope of application.

Most parallel DAC circuits are based on the summation of currents, the strength of each of which is proportional to the weight of the digital binary bit, and only the bit currents whose value is equal to 1 should be summed. For example, suppose you want to convert a four-bit binary code into an analog current signal. The weight of the fourth, most significant digit (MSD) will be 2 3 =8, the third digit - 2 2 =4, the second - 2 1 =2 and the least significant (LSB) - 2 0 =1. If the weight of the SZR I MZR = 1 mA, then I SZR = 8 mA, and the maximum output current of the converter I out.max = 15 mA and corresponds to code 1111 2. It is clear that code 1001 2, for example, will correspond to I out = 9 mA, etc. Consequently, it is necessary to construct a circuit that ensures generation and switching of precise weighing currents according to given laws. The simplest circuit that implements this principle is shown in Fig. 3.

The resistance of the resistors is chosen so that when the switches are closed, a current corresponding to the weight of the discharge flows through them. The key must be closed when the corresponding bit of the input word is equal to one. The output current is determined by the relation

With a high bit capacity of the DAC, the current-setting resistors must be matched with high accuracy. The most stringent accuracy requirements are imposed on resistors of the highest digits, since the spread of currents in them should not exceed the current of the low-order digit. Therefore, the spread of resistance in the kth discharge should be less than

From this condition it follows that the spread of the resistor resistance, for example, in the fourth digit should not exceed 3%, and in the 10th digit - 0.05%, etc.

The considered scheme, for all its simplicity, has a whole bunch of disadvantages. Firstly, for different input codes, the current consumed from the reference voltage source (RPS) will be different, and this will affect the value of the output voltage RES. Secondly, the resistance values of weight resistors can differ by thousands of times, and this makes it very difficult to implement these resistors in semiconductor ICs. In addition, the resistance of the high-order resistors in multi-bit DACs can be comparable to the resistance of the closed switch, and this will lead to a conversion error. Thirdly, in this circuit, significant voltage is applied to the open switches, which complicates their construction.

These shortcomings were eliminated in the AD7520 DAC circuit (domestic analogue of 572PA1), developed by Analog Devices in 1973, which is now essentially an industry standard (many serial DAC models are made according to it). The indicated diagram is shown in Fig. 4. MOS transistors are used here as switches.

Rice. 4. DAC circuit with switches and constant impedance matrix

In this circuit, the setting of the weighting coefficients of the converter stages is carried out by sequentially dividing the reference voltage using a resistive matrix of constant impedance. The main element of such a matrix is a voltage divider (Fig. 5), which must satisfy the following condition: if it is loaded with resistance R n, then its input resistance R in must also take the value R n. The chain weakening coefficient a=U 2 /U 1 at this load must have a given value. When these conditions are met, we obtain the following expressions for resistances:

With binary coding a =0.5. If we put R n =2R, then R s =R and R p =2R in accordance with Fig.4.

Since in any position of the switches S k they connect the lower terminals of the resistors to the common circuit bus, the reference voltage source is loaded with a constant input resistance Rin =R. This ensures that the reference voltage remains unchanged for any DAC input code.

According to Fig. 4, the output currents of the circuit are determined by the relations

and the input current

Since the lower terminals of the resistors 2R of the matrix, in any state of the switches S k, are connected to the common circuit bus through the low resistance of the closed switches, the voltages on the switches are always small, within a few millivolts. This simplifies the construction of switches and control circuits and allows the use of reference voltages from a wide range, including different polarities. Since the output current of the DAC depends linearly on U op (see (8)), converters of this type can be used to multiply the analog signal (applying it to the reference voltage input) by a digital code. Such DACs are called multiplying DACs (MDACs).

The accuracy of this circuit is reduced by the fact that for DACs with a high bit capacity, it is necessary to match the resistance R 0 of the switches with the bit currents. This is especially important for high-order keys. For example, in the 10-bit AD7520 DAC, the key MOS transistors of the six most significant bits are made different in area and their resistance R0 increases according to the binary code (20, 40, 80, : , 640 Ohms). In this way, the voltage drops across the switches of the first six bits are equalized (up to 10 mV), which ensures monotonicity and linearity of the DAC transient response. The 12-bit DAC 572PA2 has a differential nonlinearity of up to 0.025% (1 LSB).

DACs based on MOS switches have relatively low performance due to the large input capacitance of the MOS switches. The same 572PA2 has a settling time of the output current when changing the input code from 000...0 to 111...1, equal to 15 μs. The Burr-Braun 12-bit DAC7611 has an output voltage settling time of 10 µs. At the same time, DACs based on MOS switches have minimal power consumption. The same DAC7611 consumes only 2.5 mW. Recently, DAC models of the type discussed above have appeared with higher performance. Thus, the 12-bit AD7943 has a current settling time of 0.6 μs and a power consumption of only 25 μW. Low self-consumption allows such micro-power DACs to be powered directly from the reference voltage source. Moreover, they may not even have a pin for connecting an ION, for example, AD5321.

DAC on current sources

DACs based on current sources have higher accuracy. Unlike the previous version, in which the weight currents are formed by resistors of relatively low resistance and, as a result, depend on the resistance of the switches and the load, in this case the weight currents are provided by transistor current sources with high dynamic resistance. A simplified circuit of a DAC using current sources is shown in Fig. 6.

Rice. 6. DAC circuit on current sources

The weight currents are generated using a resistive matrix. The potentials of the bases of the transistors are the same, and in order for the potentials of the emitters of all transistors to be equal, the areas of their emitters are made different in accordance with the weighting coefficients. The right resistor of the matrix is not connected to the common bus, as in the diagram in Fig. 4, and to two identical transistors VT 0 and VT n connected in parallel, as a result of which the current through VT 0 is equal to half the current through VT 1. The input voltage for the resistive matrix is created using the reference transistor VT op and the operational amplifier OU1, the output voltage of which is set such that the collector current of the transistor VT op takes the value I op. Output current for N-bit DAC

Typical examples of DACs based on current switches with bipolar transistors as switches are the 12-bit 594PA1 with a settling time of 3.5 μs and a linearity error of no more than 0.012% and the 12-bit AD565, which has a settling time of 0.2 μs with the same linearity error. The AD668 has even higher performance, with a settling time of 90 ns and the same linearity error. Among the new developments, we can note the 14-bit AD9764 with a settling time of 35 ns and a linearity error of no more than 0.01%. Bipolar differential stages in which transistors operate in active mode are often used as current switches S k. This allows the settling time to be reduced to a few nanoseconds. The current switch circuit for differential amplifiers is shown in Fig. 7.

Differential cascades VT 1 -VT 3 and VT" 1 -VT" 3 are formed from standard ESL valves. The current I k flowing through the collector terminal of the output emitter follower is the output current of the cell. If a high level voltage is applied to the digital input D k, then transistor VT 3 opens and transistor VT" 3 closes. The output current is determined by the expression

The accuracy increases significantly if the resistor R e is replaced by a direct current source, as in the circuit in Fig. 6. Due to the symmetry of the circuit, it is possible to generate two output currents - direct and inverse. The fastest models of such DACs have ESL input levels. An example is the 12-bit MAX555, which has a settling time of 4 ns to the 0.1% level. Since the output signals of such DACs cover the radio frequency range, they have an output impedance of 50 or 75 ohms, which must be matched to the characteristic impedance of the cable connected to the output of the converter.

DAC APPLICATION

Schemes for the use of digital-to-analog converters relate not only to the field of code-to-analog conversion. Using their properties, you can determine the products of two or more signals, build function dividers, analog links controlled by microcontrollers, such as attenuators, integrators. Signal generators, including arbitrary waveforms, are also an important area of application for DACs. Below are some signal processing circuits that include D-A converters.

Handling signed numbers

Until now, when describing digital-to-analog converters, input digital information was represented in the form of natural numbers (unipolar). Processing integers (bipolar) has certain features. Typically, binary integers are represented using two's complement code. In this way, using eight digits, you can represent numbers in the range from -128 to +127. When entering numbers into the DAC, this range of numbers is shifted to 0...255 by adding 128. Numbers greater than 128 are considered positive, and numbers less than 128 are considered negative. The average number 128 corresponds to zero. This representation of signed numbers is called a shifted code. Adding a number that is half the full scale of a given bit (in our example it is 128) can be easily done by inverting the most significant (sign) bit. The correspondence of the considered codes is illustrated in Table. 1.

Table 1

Relationship between digital and analog quantities

To obtain an output signal with the correct sign, it is necessary to reverse shift by subtracting the current or voltage that is half the scale of the converter. This can be done in different ways for different types of DACs. For example, with DACs based on current sources, the range of variation of the reference voltage is limited, and the output voltage has a polarity opposite to the polarity of the reference voltage. In this case, the bipolar mode is most simply implemented by including an additional bias resistor R cm between the DAC output and the reference voltage input (Fig. 8a). Resistor R cm is manufactured on an IC chip. Its resistance is chosen such that the current I cm is half the maximum value of the DAC output current.

In principle, the problem of output current bias can be solved similarly for DACs based on MOS switches. To do this, you need to invert the reference voltage, and then generate a bias current from -U op, which should be subtracted from the DAC output current. However, to maintain temperature stability, it is better to ensure that the bias current is generated directly in the DAC. To do this, in the diagram in Fig. 8a, a second operational amplifier is introduced and the second output of the DAC is connected to the input of this op-amp (Fig. 8b).

Second DAC output current,

At the input of op-amp1, the current I" out is summed with the current I mr, corresponding to the unit of the least significant digit of the input code.

The total current is inverted. The current flowing through the feedback resistor R os OU2 is

and when

In the case of N=8, this coincides with the data in table up to a factor of 2. 6, taking into account the fact that for a converter based on MOS switches the maximum output current

If resistors R2 are well matched in resistance, then an absolute change in their value with temperature fluctuations does not affect the output voltage of the circuit.

For digital-to-analog converters with an output signal in the form of voltage, built on an inverse resistive matrix (see Fig. 9), the bipolar mode can be more easily implemented (Fig. 8c). Typically, such DACs contain an on-chip output buffer amplifier. To operate the DAC in a unipolar connection, the free terminal of the lower resistor R in the circuit is not connected, or is connected to a common point in the circuit to double the output voltage. To operate in a bipolar connection, the free output of this resistor is connected to the reference voltage input of the DAC. In this case, the op-amp operates in differential connection and its output voltage

As mentioned above, D-A converters based on MOS switches allow changes in the reference voltage within a wide range, including a change in polarity. The DAC output voltage is proportional to the product of the reference voltage and the input digital code. This circumstance makes it possible to directly use such DACs to multiply an analog signal by a digital code.

When the DAC is connected unipolarly, the output signal is proportional to the product of a bipolar analog signal and a unipolar digital code. Such a multiplier is called a two-quadrant multiplier. When the DAC is connected bipolarly (Fig. 8b and 8c), the output signal is proportional to the product of a bipolar analog signal and a bipolar digital code. This circuit can work as a four-quadrant multiplier.

Dividing the input voltage by a digital scale M D =D/2 N is performed using a two-quadrant divider circuit (Fig. 9).

In the diagram in Fig. 9a, a MOS switch converter with a current output operates as a voltage-to-current converter controlled by the D code and included in the op-amp feedback circuit. The input voltage is applied to the free terminal of the DAC feedback resistor located on the IC chip.

In this circuit, the output current of the DAC is

that when the condition R os = R is fulfilled, it gives

It should be noted that with the code "all zeros" the feedback is opened. This mode can be prevented by either disabling such code in software, or by connecting a resistor with a resistance equal to R·2 N+1 between the output and the inverting input of the op-amp.

A divider circuit based on a DAC with a voltage output built on an inverse resistive matrix and including a buffer op-amp is shown in Fig. 9b. The output and input voltages of this circuit are related by the equation

this implies .

In this circuit, the amplifier is covered by both positive and negative feedback. For negative feedback to prevail (otherwise the op-amp will turn into a comparator), condition D must be met<2 N-1 или M D <1/2. Это ограничивает значение входного кода нижней половиной шкалы.

DAC PARAMETERS

With a sequential increase in the values of the input digital signal D(t) from 0 to 2 N -1 through the least significant unit (EMP), the output signal U out (t) forms a stepped curve. This dependence is usually called the DAC conversion characteristic. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (Fig. 10), which corresponds to the ideal transformation characteristic. The actual transformation characteristic may differ significantly from the ideal one in terms of the size and shape of the steps, as well as their location on the coordinate plane. There are a number of parameters to quantify these differences.

Rice. 10 Static characteristics of DAC conversion

Static parameters

Resolution - increment U out when converting adjacent values D j, i.e. different on the EMR. This increment is the quantization step. For binary conversion codes, the nominal value of the quantization step is h=U psh /(2 N -1), where U psh is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit capacity of the DAC. The higher the bit capacity of the converter, the higher its resolution. Full scale error is the relative difference between the actual and ideal values of the conversion scale limit in the absence of zero offset.

It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.

Zero offset error - the value of U out when the DAC input code is zero. It is an additive component of the total error. Typically stated in millivolts or as a percentage of full scale:

Nonlinearity is the maximum deviation of the actual conversion characteristic U out (D) from the optimal one (line 2 in Fig. 10). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Nonlinearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristics shown in Fig. 10

Differential nonlinearity is the maximum change (taking into account the sign) of the deviation of the actual transformation characteristic U out (D) from the optimal one when moving from one input code value to another adjacent value. Usually defined in relative units or in EMP. For the characteristics shown in Fig. 10,

The monotonicity of the conversion characteristic is an increase (decrease) in the output voltage of the DAC U out with an increase (decrease) in the input code D. If the differential nonlinearity is greater than the relative quantization step h/U psh, then the converter characteristic is non-monotonic.

The temperature instability of a DA converter is characterized by the temperature coefficients of full scale error and zero offset error.

Full scale and zero offset errors can be corrected by calibration (tuning). Nonlinearity errors cannot be eliminated by simple means.

The dynamic parameters of the DAC are determined by the change in the output signal when the input code changes abruptly, usually from the value “all zeros” to “all ones” (Fig. 11).

Rice. 11. DAC transient response

Establishment time is the time interval from the moment the input code changes (in Fig. 11 t=0) until the moment when the equality is satisfied for the last time

|U out -U psh |=d/2,

with d/2 usually corresponding to EMP.

Slew rate - the maximum rate of change of U out (t) during the transient process. It is defined as the ratio of the increment DU out to the time Dt during which this increment occurred. Usually specified in the technical specifications of a DAC with a voltage output signal. For a DAC with a current output, this parameter largely depends on the type of output op-amp.

For voltage-output multiplying DACs, the unity gain frequency and power bandwidth are often specified, which are largely determined by the properties of the output amplifier.

LIST OF REFERENCES USED

1. Federkov B.G., Telets V.A., DAC and ADC microcircuits: operation, parameters, application. M.: Energoizdat, 1990. –320 p.

2. Valakh V.V., Grigoriev V.F., High-speed ADCs for measuring the shape of random signals M.: Instruments and experimental equipment. 1987. No. 4 p.86-90

3. High-speed integrated circuits DAC and ADC and measurement of their parameters. Edited by Marcinkavyuches. M.: Radio and communications. 1988 –224 pp.©

Analogue signals are characterized by many technical parameters, one of which is: For example, the human ear hears signals having a frequency in the range from 1 to 22 kHz, and visible light contains frequencies measured in billions of hertz. An example of recording an analog signal is a gramophone record. Photographs, first black and white, and then color, are also an example of recording an analog signal.

It’s almost always worth saying a few words about it afterward, so that the task that the devices we are considering is solved is clearer.

ADC converts to digital. Typically, the number that corresponds to the magnitude of the signal at the time of its measurement is represented in binary code. Each measurement is performed at a specific frequency, called the quantization frequency.

The minimum quantization frequency that ensures undistorted signal reconstruction is theoretically justified. This signal is without distortion and should be restored at the output of the digital-to-analog converter. The quantization frequency must be at least two maximum frequencies of the converted signal. For example, for undistorted conversion of an audio signal, a quantization frequency of 44 kHz is sufficient.

Now it is clear that it has a sequence of binary codes at the input, which it must convert into the corresponding analog signal.

Operational reliability and service life are also included in the indicators, but these parameters do not depend on the operating principle of the DAC, but rather on the element base and build quality. Regardless of the conversion principle, digital-to-analog converters are distinguished by characteristics such as dynamic range, conversion accuracy and timing.

The dynamic range is determined for the input and output of the DAC as the ratio of the maximum value at the input (output) to the minimum input (output) value.

One of the time parameters is the reciprocal of the quantization frequency, called the quantization period. It is clear that for a DAC this value is set by the ADC with which the signal was converted.

The main quantity characterizing the performance of the DAC is the conversion time. Here you have to choose: longer conversion time means a more accurate DAC, but its speed is lower, and vice versa.

Let's look at some principles of digital-to-analog conversion, without giving formulas and diagrams. There are two principles of conversion - sequential and parallel.

The digital-to-analog converter converts the sequence of digital codes at the input into a sequence of rectangular pulses at the output. The pulse width and the subsequent interval until the next pulse are determined depending on the value of the incoming binary code. Consequently, at the output of the low-pass filter, an analog signal is obtained from pulses arriving at the input with a variable period.

Parallel conversion is performed, for example, using resistors connected in parallel to a stable power source. The number of resistances is equal to the bit depth of the code arriving at the input. The resistance value in the high-order category is 2 times less than in the previous low-order category. There is a key in the circuit of each resistance. The input code controls the keys - where 1 is, current flows. Consequently, in the circuits the current will be determined by the weight of the discharge, and the digital-to-analog converter at the output has a total current that will correspond to the recorded binary code.

Between the discrete digital world and analog signals.

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Application

The DAC is used whenever it is necessary to convert a signal from a digital representation to an analogue one, for example, in CD players (Audio CD).

DAC types

The most common types of electronic DACs are:

Pulse width modulator- the simplest type of DAC. A stable source of current or voltage is periodically turned on for a time proportional to the digital code being converted, then the resulting pulse sequence is filtered by an analog low-pass filter. This method is often used to control the speed of electric motors, and is also becoming popular in Hi-Fi audio equipment;

Oversampling DAC, such as delta-sigma DACs, are based on variable pulse density. Oversampling allows you to use a DAC with a lower bit depth to achieve a higher bit depth of the final conversion; Often a delta-sigma DAC is built on the basis of a simple one-bit DAC, which is practically linear. A low-bit DAC receives a pulse signal with pulse density modulated(with a constant pulse duration, but with a variable duty cycle), created using negative feedback. Negative feedback acts as a high-pass filter for quantization noise.

Most large-bit DACs (more than 16 bits) are built on this principle due to its high linearity and low cost. The speed of the delta-sigma DAC reaches hundreds of thousands of samples per second, the bit depth is up to 24 bits. To generate a pulse density modulated signal, a simple first order or higher order delta-sigma modulator such as MASH (Multi stage noise SHaping) can be used. Increasing the resampling frequency softens the requirements for the output low-pass filter and improves quantization noise suppression;

Weighing type DAC, in which each bit of the converted binary code corresponds to a resistor or current source connected to a common summation point. The source current (conductivity of the resistor) is proportional to the weight of the bit to which it corresponds. Thus, all non-zero bits of the code are added to the weight. The weighing method is one of the fastest, but it is characterized by low accuracy due to the need for a set of many different precision sources or resistors and variable impedance. For this reason, weighing DACs have a maximum width of eight bits;

Characteristics

DACs are located at the beginning of the analog path of any system, so the parameters of the DAC largely determine the parameters of the entire system as a whole. The following are the most important characteristics of a DAC.

Maximum sampling rate- the maximum frequency at which the DAC can operate, producing the correct result at the output. In accordance with Kotelnikov's theorem, to correctly reproduce an analog signal from a digital form, it is necessary that the sampling frequency be no less than twice the maximum frequency in the signal spectrum. For example, to reproduce the entire human-audible audio frequency range, the spectrum of which extends up to 20 kHz, it is necessary that the audio signal be sampled at a frequency of at least 40 kHz. The Audio CD standard sets the audio sampling frequency to 44.1 kHz; To reproduce this signal you will need a DAC capable of operating at this frequency. In cheap computer sound cards, the sampling frequency is 48 kHz. Signals sampled at other frequencies are resampled to 48 kHz, which partially degrades the signal quality.

Static characteristics:
- DNL (differential nonlinearity) - characterizes how much the analog signal increment obtained by increasing the code by 1 least significant bit (LSB) differs from the correct value;
- INL (integral nonlinearity) - characterizes how much the transfer characteristic of the DAC differs from the ideal one. The ideal characteristic is strictly linear; INL shows how far the voltage at the DAC output for a given code is from the linear characteristic; expressed in minimum wage;
- gain;
- bias.

Frequency characteristics:
- SNDR (signal-to-noise ratio + distortion) - characterizes in decibels the ratio of the output signal power to the total power of noise and harmonic distortion;
- HDi (i-th harmonic coefficient) - characterizes the ratio of the i-th harmonic to the fundamental harmonic;
- THD (harmonic distortion) is the ratio of the total power of all harmonics (except the first) to the power of the first harmonic.

Analog-to-digital converter(ADC, English Analog-to-digital converter, ADC) is a device that converts an input analog signal into a discrete code (digital signal). The reverse conversion is done using a DAC (Digital to Analogue Converter, DAC).

Typically, an ADC is an electronic device that converts voltage into binary digital code. However, some non-electronic devices with a digital output should also be classified as ADCs, such as some types of angle-to-code converters. The simplest single-bit binary ADC is the comparator.

Permission

The resolution of an ADC—the minimum change in the magnitude of an analog signal that can be converted by a given ADC—is related to its bit capacity. In the case of a single measurement without taking into account noise, the resolution is directly determined by the bit capacity of the ADC.

The ADC capacity characterizes the number of discrete values that the converter can produce at the output. In binary ADCs it is measured in bits, in ternary ADCs it is measured in trits. For example, a binary 8-bit ADC is capable of producing 256 discrete values (0...255), since , a ternary 8-bit ADC is capable of producing 6561 discrete values, since .

Voltage resolution is equal to the difference between the voltages corresponding to the maximum and minimum output code, divided by the number of output discrete values. For example:

Input range = 0 to 10 volts

Binary ADC capacity 12 bits: 212 = 4096 quantization levels

Binary ADC voltage resolution: (10-0)/4096 = 0.00244 volts = 2.44 mV

Bit capacity of ternary ADC 12 trit: 312 = 531,441 quantization level

Ternary ADC voltage resolution: (10-0)/531441 = 0.0188 mV = 18.8 µV

Input range = −10 to +10 volts

Binary ADC capacity 14 bits: 214 = 16384 quantization levels

Binary ADC voltage resolution: (10-(-10))/16384 = 20/16384 = 0.00122 volts = 1.22 mV

Bit capacity of ternary ADC 14 trit: 314 = 4,782,969 quantization levels

Ternary ADC voltage resolution: (10-(-10))/4782969 = 0.00418 mV = 4.18 µV

In practice, the resolution of an ADC is limited by the signal-to-noise ratio of the input signal. When the noise intensity at the ADC input is high, distinguishing between adjacent input signal levels becomes impossible, that is, the resolution deteriorates. In this case, the actually achievable resolution is described by the effective number of bits (ENOB), which is less than the actual bit capacity of the ADC. When converting a highly noisy signal, the low-order bits of the output code are practically useless, since they contain noise. To achieve the declared bit depth, the S/N ratio of the input signal must be approximately 6 dB for each bit of bit depth (6 dB corresponds to a fourfold change in signal level).

Conversion Types

According to the method of algorithms used, ADCs are divided into:

Sequential direct search

Successive approximation

Serial with sigma-delta modulation

Parallel single stage

Parallel two- or more-stage (conveyor)

The transfer characteristic of an ADC is the dependence of the numerical equivalent of the output binary code on the magnitude of the input analog signal. They talk about linear and nonlinear ADCs. This division is conditional. Both transmission characteristics are stepped. But for “linear” ADCs it is always possible to draw a straight line such that all points of the transfer characteristic corresponding to the input values delta*2^k (where delta is the sampling step, k lies in the range 0..N, where N is the ADC bit depth) are equidistant from it.

Accuracy

There are several sources of ADC error. Quantization errors and (assuming that the ADC must be linear) nonlinearities are inherent in any analog-to-digital conversion. In addition, there are so-called aperture errors that are a consequence of jitter of the clock generator; they appear when converting the signal as a whole (and not just one sample).

These errors are measured in units called LSB - least significant bit. In the above example of an 8-bit binary ADC, the error in 1 LSB is 1/256 of the full signal range, that is, 0.4%, in the 5-trit ternary ADC, the error in 1 LSB is 1/243 of the full signal range, that is 0.412%, in an 8-trite ternary ADC, the error in 1 LSB is 1/6561, that is, 0.015%.

Types of ADCs

The following are the main methods for constructing electronic ADCs:

Direct conversion ADC:

Parallel direct conversion ADCs, which are fully parallel ADCs, contain one comparator for each discrete input signal level. At any time, only comparators corresponding to levels below the input signal level produce an excess signal at their output. Signals from all comparators go either directly to a parallel register, then the code is processed in software, or to a hardware logic encoder, which generates the required digital code in hardware depending on the code at the encoder input. Data from the encoder is recorded in a parallel register. The sampling rate of parallel ADCs, in general, depends on the hardware characteristics of the analog and logic elements, as well as on the required sampling rate.

Parallel direct conversion ADCs are the fastest, but usually have a resolution of no more than 8 bits, as they entail large hardware costs (comparators). ADCs of this type have a very large chip size, high input capacitance, and can produce short-term errors at the output. Often used for video or other high-frequency signals, they are also widely used in industry to monitor fast-changing processes in real time.

Pipeline operation of ADCs is used in parallel-serial ADCs of direct conversion, in contrast to the usual mode of operation of parallel-serial ADCs of direct conversion, in which data is transmitted after complete conversion; in pipeline operation, data of partial conversions is transmitted as soon as it is ready until the end of the full conversion.

A successive approximation ADC, or bit-balanced ADC, contains a comparator, an auxiliary DAC, and a successive approximation register. The ADC converts the analog signal to a digital signal in N steps, where N is the ADC bit depth. At each step, one bit of the desired digital value is determined, starting from the SZR and ending with the LZR. The sequence of actions to determine the next bit is as follows. The auxiliary DAC is set to an analog value formed from the bits already determined in the previous steps; the bit that must be determined at this step is set to 1, the lower bits are set to 0. The value obtained at the auxiliary DAC is compared with the input analog value. If the value of the input signal is greater than the value on the auxiliary DAC, then the bit to be determined gets the value 1, otherwise 0. Thus, determining the final digital value resembles a binary search. This type of ADC has both high speed and good resolution. However, in the absence of a storage sampling device, the error will be much larger (imagine that after the largest digit was digitized, the signal began to change).

Differential encoding ADCs (delta-encoded ADCs) contain a reverse counter, the code from which is sent to the auxiliary DAC. The input signal and the signal from the auxiliary DAC are compared using a comparator. Thanks to negative feedback from the comparator to the counter, the code on the counter is constantly changing so that the signal from the auxiliary DAC differs as little as possible from the input signal. After some time, the signal difference becomes less than the minimum value, and the counter code is read as the output digital signal of the ADC. ADCs of this type have a very large input signal range and high resolution, but the conversion time depends on the input signal, although it is limited from above. In the worst case, the conversion time is equal to Tmax=(2q)/fс, where q is the ADC bit capacity, fс is the frequency of the counter clock generator. Differential encoding ADCs are usually a good choice for digitizing real-world signals, since most signals in physical systems are not prone to abrupt changes. Some ADCs use a combined approach: differential coding and successive approximation; this works especially well in cases where the high-frequency components in the signal are known to be relatively small.

Comparison ADCs with a sawtooth signal (some ADCs of this type are called Integrating ADCs, they also include serial counting ADCs) contain a sawtooth voltage generator (in a serial counting ADC a step voltage generator consisting of a counter and a DAC), a comparator and a time counter. The sawtooth signal increases linearly from the lower to the upper level, then quickly falls to the lower level. At the moment the rise begins, the time counter starts. When the ramp signal reaches the input signal level, the comparator is triggered and stops the counter; the value is read from the counter and supplied to the ADC output. This type of ADC is the simplest in structure and contains the minimum number of elements. At the same time, the simplest ADCs of this type have rather low accuracy and are sensitive to temperature and other external parameters. To increase accuracy, a ramp generator can be built around a counter and an auxiliary DAC, but this structure has no other advantages over successive approximation ADCs and differential encoding ADCs.

ADCs with charge balancing (these include ADCs with two-stage integration, ADCs with multi-stage integration, and some others) contain a stable current generator, a comparator, a current integrator, a clock generator, and a pulse counter. The transformation occurs in two stages (two-stage integration). In the first stage, the input voltage value is converted into a current (proportional to the input voltage), which is supplied to the current integrator, the charge of which is initially zero. This process lasts for a time TN, where T is the period of the clock generator, N is a constant (a large integer that determines the charge accumulation time). After this time, the integrator input is disconnected from the ADC input and connected to a stable current generator. The polarity of the generator is such that it reduces the charge accumulated in the integrator. The discharge process continues until the charge in the integrator decreases to zero. The discharge time is measured by counting clock pulses from the moment the discharge begins until the integrator reaches zero charge. The calculated number of clock pulses will be the ADC output code. It can be shown that the number of pulses n, counted during the discharge time, is equal to: n=UinN(RI0)−1, where Uin is the input voltage of the ADC, N is the number of pulses of the accumulation stage (defined above), R is the resistance of the resistor that converts the input voltage into current, I0 is the value of the current from the stable current generator, discharging the integrator at the second stage. Thus, potentially unstable system parameters (primarily the capacitance of the integrator capacitor) are not included in the final expression. This is a consequence of the two-stage process: the errors introduced in the first and second stages are mutually subtracted. There are no strict requirements even for the long-term stability of the clock generator and the comparator bias voltage: these parameters must be stable only for a short time, that is, during each conversion (no more than 2TN). In fact, the principle of two-stage integration allows the ratio of two analog quantities (input and reference current) to be directly converted into a ratio of numeric codes (n and N in terms defined above) with virtually no additional errors introduced. The typical width of this type of ADC is 10 to 18 bits. An additional advantage is the ability to build converters that are insensitive to periodic interference (for example, interference from the mains supply) due to the precise integration of the input signal over a fixed time interval. The disadvantage of this type of ADC is the low conversion speed. Charge balancing ADCs are used in high precision measuring instruments.

ADC with intermediate conversion to pulse repetition rate. The signal from the sensor passes through a level converter and then through a voltage-frequency converter. Thus, the input of the logic circuit itself receives a signal whose characteristic is only the pulse frequency. The logical counter receives these pulses as input during the sampling time, thus producing at the end of the sampling time a code combination numerically equal to the number of pulses received by the converter during the sampling time. Such ADCs are quite slow and not very accurate, but are nevertheless very simple to implement and therefore have a low cost.

Sigma-delta ADCs (also called delta-sigma ADCs) perform analog-to-digital conversion at a sampling rate many times higher than required and, through filtering, leave only the desired spectral band in the signal.

Non-electronic ADCs are usually built on the same principles.

Commercial ADCs

As a rule, they are produced in the form of microcircuits.

For most ADCs, the bit depth ranges from 6 to 24 bits, and the sampling frequency is up to 1 MHz. Mega- and gigahertz ADCs are also available (February 2002). Megahertz ADCs are required in digital video cameras, video capture devices, and digital TV tuners to digitize the complete video signal. Commercial ADCs typically have an output error of ±0.5 to ±1.5 LSB.

One of the factors that increases the cost of chips is the number of pins, since they force the chip package to be larger, and each pin must be attached to the die. To reduce the number of pins, ADCs operating at low sampling rates often have a serial interface. The use of an ADC with a serial interface often allows for increased packing density and a smaller board area.

Often ADC chips have several analog inputs connected within the chip to a single ADC through an analog multiplexer. Various ADC models may include sample-and-hold devices, instrumentation amplifiers, or high-voltage differential input and other similar circuits.

Other Applications

Analog-to-digital conversion is used wherever an analog signal needs to be received and processed in digital form.

Special video ADCs are used in computer TV tuners, video input cards, and video cameras for digitizing video signals. Microphone and line audio inputs of computers are connected to an audio ADC.

ADCs are an integral part of data acquisition systems.

Successive approximation ADCs with a capacity of 8-12 bits and sigma-delta ADCs with a capacity of 16-24 bits are built into single-chip microcontrollers.

Very fast ADCs are needed in digital oscilloscopes (parallel and pipeline ADCs are used)

Modern scales use ADCs with a resolution of up to 24 bits, which convert the signal directly from the strain gauge sensor (sigma-delta ADC).

ADCs are part of radio modems and other radio data transmission devices, where they are used together with a DSP processor as a demodulator.

Ultra-fast ADCs are used in base station antenna systems (in so-called SMART antennas) and in radar antenna arrays.

Digital-to-analog converter (DAC) - a device for converting digital (usually binary) code into an analog signal (current, voltage or charge). Digital-to-analog converters are the interface between the discrete digital world and analog signals.

An analog-to-digital converter (ADC) performs the reverse operation.

An audio DAC usually receives a digital signal in pulse-code modulation (PCM, pulse-code modulation) as its input. The task of converting various compressed formats to PCM is performed by the respective codecs.

Application

The DAC is used whenever it is necessary to convert a signal from a digital representation to an analogue one, for example, in CD players (Audio CD).

DAC types

The most common types of electronic DACs are:

A pulse width modulator is the simplest type of DAC. A stable source of current or voltage is periodically turned on for a time proportional to the digital code being converted, then the resulting pulse sequence is filtered by an analog low-pass filter. This method is often used to control the speed of electric motors, and is also becoming popular in Hi-Fi audio;

Oversampling DACs, such as delta-sigma DACs, are based on variable pulse density. Oversampling allows you to use a DAC with a lower bit depth to achieve a higher bit depth of the final conversion; Often a delta-sigma DAC is built on the basis of a simple one-bit DAC, which is practically linear. A low-bit DAC receives a pulse signal with modulated pulse density (with a constant pulse duration, but with a variable duty cycle), created using negative feedback. Negative feedback acts as a high-pass filter for quantization noise.

A weighing-type DAC in which each bit of the converted binary code corresponds to a resistor or current source connected to a common summation point. The source current (conductivity of the resistor) is proportional to the weight of the bit to which it corresponds. Thus, all non-zero bits of the code are added to the weight. The weighing method is one of the fastest, but it is characterized by low accuracy due to the need for a set of many different precision sources or resistors and variable impedance. For this reason, weighing DACs have a maximum width of eight bits;

Ladder-type DAC (chain R-2R circuit). In the R-2R-DAC, values are created in a special circuit consisting of resistors with resistances R and 2R, called a constant impedance matrix, which has two types of connection: direct - current matrix and inverse - voltage matrix. The use of identical resistors can significantly improve accuracy compared to a conventional weighing DAC, since it is relatively simple to produce a set of precision elements with the same parameters. DACs of the R-2R type allow you to push back the limitations on bit depth. With laser trimming of resistors on one substrate, an accuracy of 20-22 bits is achieved. Most of the conversion time is spent in the operational amplifier, so it must be as fast as possible. The speed of the DAC is a few microseconds or less (that is, nanoseconds);

Characteristics

Bit depth is the number of different output signal levels that the DAC can reproduce. Typically specified in bits; the number of bits is the base 2 logarithm of the number of levels. For example, a one-bit DAC is capable of reproducing two () levels, and an eight-bit DAC can reproduce 256 () levels. The bit depth is closely related to the effective number of bits (ENOB, Effective Number of Bits), which shows the actual resolution achievable on a given DAC.

The maximum sampling frequency is the maximum frequency at which the DAC can operate, producing the correct result at the output. According to the Nyquist-Shannon theorem (also known as the Kotelnikov theorem), to correctly reproduce an analog signal from a digital form, the sampling frequency must be no less than twice the maximum frequency in the signal spectrum. For example, to reproduce the entire human-audible audio frequency range, the spectrum of which extends up to 20 kHz, it is necessary that the audio signal be sampled at a frequency of at least 40 kHz. The Audio CD standard sets the audio sampling rate to 44.1 kHz; To reproduce this signal you will need a DAC capable of operating at this frequency. Cheap computer sound cards have a sampling rate of 48 kHz. Signals sampled at other frequencies are resampled to 48 kHz, which partially degrades the signal quality.

Monotonicity is the property of a DAC to increase the analog output signal as the input code increases.

THD+N (total harmonic distortion + noise) is a measure of distortion and noise introduced into the signal by the DAC. Expressed as a percentage of the harmonic power and noise in the output signal. An important parameter for small-signal DAC applications.

Dynamic range is the ratio of the largest and smallest signals that a DAC can reproduce, expressed in decibels. This parameter is related to the bit depth and noise threshold.

Static characteristics:

DNL (differential nonlinearity) - characterizes how much the analog signal increment obtained by increasing the code by 1 least significant bit (LSB) differs from the correct value;

INL (integral nonlinearity) - characterizes how much the transfer characteristic of the DAC differs from the ideal one. The ideal characteristic is strictly linear; INL shows how far the voltage at the DAC output for a given code is from the linear characteristic; expressed in minimum wage;

gain;

bias.

Frequency characteristics:

SNDR (signal-to-noise + distortion ratio) - characterizes in decibels the ratio of the output signal power to the total power of noise and harmonic distortion;

HDi (i-th harmonic coefficient) - characterizes the ratio of the i-th harmonic to the fundamental harmonic;

THD (harmonic distortion factor) - the ratio of the total power of all harmonics (except the first) to the power of the first harmonic

Digital-to-analog converters have static and dynamic characteristics.

Static characteristics of the DAC

Main static characteristics DACs are:

· resolution;

· nonlinearity;

· differential nonlinearity;

· monotony;

· conversion factor;

· absolute full scale error;

· relative full scale error;

· zero offset;

absolute error

Resolution – this is the increment of U OUT when transforming adjacent values D j, i.e. differing by one least significant unit (EMP). This increment is the quantization step. For binary conversion codes, the nominal value of the quantization step is

h = U PS /(2 N – 1),

where U PN is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit capacity of the DAC. The higher the bit capacity of the converter, the higher its resolution.

Full scale error – the relative difference between the real and ideal values of the conversion scale limit in the absence of a zero offset, i.e.

It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.

Zero offset error – the value of U OUT when the DAC input code is zero. It is an additive component of the total error. Typically stated in millivolts or as a percentage of full scale:

Nonlinearity – maximum deviation of the actual conversion characteristic U OUT (D) from the optimal one (Fig. 5.2, line 2). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Nonlinearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristics shown in Fig. 5.2,

Differential nonlinearity – the maximum change (taking into account the sign) of the deviation of the actual transformation characteristic U OUT (D) from the optimal one when moving from one value of the input code to another adjacent value. Usually defined in relative units or in EMP. For the characteristics shown in Fig. 5.2,

Monotone conversion characteristics - increase (decrease) of the DAC output voltage (U OUT) with an increase (decrease) of the input code D. If the differential nonlinearity is greater than the relative quantization step h/U PN, then the converter characteristic is nonmonotonic.

The temperature instability of the DAC is characterized by temperature coefficients full scale errors and zero offset errors.

Full scale and zero offset errors can be corrected by calibration (tuning). Nonlinearity errors cannot be eliminated by simple means.

Dynamic characteristics of the DAC

TO dynamic characteristics am DACs include settling time and conversion time.

With a sequential increase in the values of the input digital signal D(t) from 0 to (2 N – 1) through the least significant unit, the output signal U OUT (t) forms a step curve. This dependence is usually called the DAC conversion characteristic. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (see Fig. 5.2), which corresponds to the ideal conversion characteristic. The actual transformation characteristic may differ significantly from the ideal one in terms of the size and shape of the steps, as well as their location on the coordinate plane. There are a number of parameters to quantify these differences.

The dynamic parameters of the DAC are determined by the change in the output signal when the input code changes abruptly, usually from the value “all zeros” to “all ones” (Fig. 5.3).

Settling time – time interval from the moment of betrayal
input code (Fig. 5.3, t = 0) until the last time the equality is satisfied:

|U OUT – U ПШ | = d/2,

with d/2 usually corresponding to EMP.

Slew rate – maximum rate of change of U OUT (t) during the transient process. Defined as the increment ratio D U OUT to the time Dt during which this increment occurred. Usually specified in the technical specifications of a DAC with a voltage output signal. For digital-to-analog converters with current output, this parameter largely depends on the type of output op-amp.

For voltage-output multiplying DACs, the unity gain frequency and power bandwidth are often specified, which are largely determined by the properties of the output amplifier.

Figure 5.4 shows two linearization methods, from which it follows that the linearization method for obtaining the minimum value of D l, shown in Fig. 5.4, b, allows you to reduce the error D l by half compared to the linearization method at boundary points (Fig. 5.4, a).

For digital-to-analog converters with n binary digits, in the ideal case (in the absence of conversion errors), the analog output U OUT is related to the input binary number as follows:

U OUT = U OP (a 1 2 -1 + a 2 2 -2 +…+ a n 2 -n),

where U OP is the reference voltage of the DAC (from the built-in or external source).

Since ∑ 2 -i = 1 – 2 -n, then with all bits turned on, the output voltage of the DAC is equal to:

U OUT (a 1 …a n) = U OP (1 – 2 -n) = (U OP /2 n) (2 n – 1) = D (2 n – 1) = U PS,

where U PN is the full scale voltage.

Thus, when all bits are turned on, the output voltage of the digital-to-analog converter, which in this case forms U PN, differs from the value of the reference voltage (U OP) by the value of the least significant digit of the converter (D), defined as

D = U OP /2 n.

When any i-th bit is turned on, the output voltage of the DAC will be determined from the relationship:

U OUT /a i = U OP 2 -i .

A digital-to-analog converter converts the digital binary code Q 4 Q 3 Q 2 Q 1 into an analog value, usually voltage U OUT. or current I OUT. Each bit of the binary code has a certain weight of the i-th bit twice as much as the weight of the (i-1)th one. The operation of the DAC can be described by the following formula:

U OUT = e (Q 1 1 + Q 2 2 + Q 3 4 + Q 4 8 +…),

where e is the voltage corresponding to the weight of the least significant digit, Q i is the value of the i-th digit of the binary code (0 or 1).

For example, the number 1001 corresponds to:

U OUT = e (1· 1 + 0 · 2 + 0 · 4 + 1 · = 9 · e,

and the number 1100 corresponds

U OUT = e (0· 1 + 0 · 2 + 1 · 4 + 1 · = 12 · e.